3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
9 #include <ppc_asm.tmpl>
13 /**************************************************************************
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
20 * Pointer to the table is returned in r1
22 *************************************************************************/
30 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
31 * use the speed up boot process. It is patched after relocation to
34 #ifndef CONFIG_NAND_SPL
35 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
37 tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
38 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
39 tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
43 * TLB entries for SDRAM are not needed on this platform.
44 * They are dynamically generated in the SPD DDR(2) detection
48 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
49 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
50 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
53 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
54 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
55 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
57 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
58 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
59 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
60 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
62 /* PCIe UTL register */
63 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
65 #if !defined(CONFIG_ARCHES)
66 /* TLB-entry for NAND */
67 tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
69 /* TLB-entry for CPLD */
70 tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
72 /* TLB-entry for FPGA */
73 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
76 /* TLB-entry for OCM */
77 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
79 /* TLB-entry for Local Configuration registers => peripherals */
80 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
82 /* AHB: Internal USB Peripherals (USB, SATA) */
83 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
85 #if defined(CONFIG_RAPIDIO)
86 /* TLB-entries for RapidIO (SRIO) */
87 tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
89 tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
91 tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
93 tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
99 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
101 * For NAND booting the first TLB has to be reconfigured to full size
102 * and with caching disabled after running from RAM!
104 #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
105 #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
106 #define TLB02 TLB2(AC_RWX | SA_IG)
112 addi r4,r0,0x0000 /* TLB entry #0 */
115 tlbwe r5,r4,0x0000 /* Save it out */
118 tlbwe r5,r4,0x0001 /* Save it out */
121 tlbwe r5,r4,0x0002 /* Save it out */