2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
3 * SPDX-License-Identifier: GPL-2.0+
6 #include <ppc_asm.tmpl>
9 #include <asm/ppc4xx.h>
11 /**************************************************************************
14 * This table is used by the cpu boot code to setup the initial tlb
15 * entries. Rather than make broad assumptions in the cpu source tree,
16 * this table lets each board set things up however they like.
18 * Pointer to the table is returned in r1
20 *************************************************************************/
28 tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
31 * TLB entries for SDRAM are not needed on this platform.
32 * They are dynamically generated in the SPD DDR(2) detection
36 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
37 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
38 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
39 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
40 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)