3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
9 #include <ppc_asm.tmpl>
16 * This table is used by the cpu boot code to setup the initial tlb
17 * entries. Rather than make broad assumptions in the cpu source tree,
18 * this table lets each board set things up however they like.
20 * Pointer to the table is returned in r1
28 /* vxWorks needs this as first entry for the Machine Check interrupt */
29 tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
32 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
33 * entry is already configured for SDRAM via the JTAG debugger and mustn't
34 * be re-initialized by this RAM-booting U-Boot version.
36 #ifndef CONFIG_SYS_RAMBOOT
37 /* TLB-entry for DDR SDRAM (Up to 2GB) */
38 #ifdef CONFIG_4xx_DCACHE
39 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
41 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
43 #endif /* CONFIG_SYS_RAMBOOT */
45 /* TLB-entry for EBC */
46 tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
48 /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
49 * speed up boot process. It is patched after relocation to enable SA_I
51 #ifndef CONFIG_NAND_SPL
52 tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
54 tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
57 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
58 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
59 tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
62 /* TLB-entry for PCI Memory */
63 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
64 tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
65 tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
66 tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
68 /* TLB-entry for NAND */
69 tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
71 /* TLB-entry for Internal Registers & OCM */
72 tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
74 /*TLB-entry PCI registers*/
75 tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
77 /* TLB-entry for peripherals */
78 tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
80 /* TLB-entry PCI IO Space - from sr@denx.de */
81 tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
85 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
87 * For NAND booting the first TLB has to be reconfigured to full size
88 * and with caching disabled after running from RAM!
90 #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
91 #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
92 #define TLB02 TLB2(AC_RWX | SA_IG)
98 addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
101 tlbwe r5,r4,0x0000 /* Save it out */
104 tlbwe r5,r4,0x0001 /* Save it out */
107 tlbwe r5,r4,0x0002 /* Save it out */