2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <spd_sdram.h>
13 #include <asm/ppc4xx-emac.h>
16 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
17 void show_reset_reg(void);
20 DECLARE_GLOBAL_DATA_PTR;
24 int board_early_init_f (void)
27 volatile unsigned int *GpioOdr;
28 volatile unsigned int *GpioTcr;
29 volatile unsigned int *GpioOr;
31 /*-------------------------------------------------------------------------+
32 | Initialize EBC CONFIG
33 +-------------------------------------------------------------------------*/
34 mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
35 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
36 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
37 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
38 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
40 /*-------------------------------------------------------------------------+
41 | 64MB FLASH. Initialize bank 0 with default values.
42 +-------------------------------------------------------------------------*/
43 mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
44 EBC_BXAP_BCE_DISABLE |
45 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
46 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
47 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
48 EBC_BXAP_BEM_WRITEONLY |
49 EBC_BXAP_PEN_DISABLED);
50 mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
51 EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
53 /*-------------------------------------------------------------------------+
54 | FPGA. Initialize bank 1 with default values.
55 +-------------------------------------------------------------------------*/
56 mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
57 EBC_BXAP_BCE_DISABLE |
58 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
59 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
60 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
61 EBC_BXAP_BEM_WRITEONLY |
62 EBC_BXAP_PEN_DISABLED);
63 mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
64 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
66 /*-------------------------------------------------------------------------+
67 | LCM. Initialize bank 2 with default values.
68 +-------------------------------------------------------------------------*/
69 mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
70 EBC_BXAP_BCE_DISABLE |
71 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
72 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
73 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
74 EBC_BXAP_BEM_WRITEONLY |
75 EBC_BXAP_PEN_DISABLED);
76 mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
77 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
79 /*-------------------------------------------------------------------------+
80 | TMP. Initialize bank 3 with default values.
81 +-------------------------------------------------------------------------*/
82 mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
83 EBC_BXAP_BCE_DISABLE |
84 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
85 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
86 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
87 EBC_BXAP_BEM_WRITEONLY |
88 EBC_BXAP_PEN_DISABLED);
89 mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
90 EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
92 /*-------------------------------------------------------------------------+
93 | Connector 4~7. Initialize bank 3~ 7 with default values.
94 +-------------------------------------------------------------------------*/
104 /*--------------------------------------------------------------------
105 * Setup the interrupt controller polarities, triggers, etc.
106 *-------------------------------------------------------------------*/
108 * Because of the interrupt handling rework to handle 440GX interrupts
109 * with the common code, we needed to change names of the UIC registers.
110 * Here the new relationship:
112 * U-Boot name 440GX name
113 * -----------------------
119 mtdcr (UIC1SR, 0xffffffff); /* clear all */
120 mtdcr (UIC1ER, 0x00000000); /* disable all */
121 mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
122 mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
123 mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
124 mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
125 mtdcr (UIC1SR, 0xffffffff); /* clear all */
127 mtdcr (UIC2SR, 0xffffffff); /* clear all */
128 mtdcr (UIC2ER, 0x00000000); /* disable all */
129 mtdcr (UIC2CR, 0x00000000); /* all non-critical */
130 mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
131 mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
132 mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
133 mtdcr (UIC2SR, 0xffffffff); /* clear all */
135 mtdcr (UIC3SR, 0xffffffff); /* clear all */
136 mtdcr (UIC3ER, 0x00000000); /* disable all */
137 mtdcr (UIC3CR, 0x00000000); /* all non-critical */
138 mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
139 mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
140 mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
141 mtdcr (UIC3SR, 0xffffffff); /* clear all */
143 mtdcr (UIC0SR, 0xfc000000); /* clear all */
144 mtdcr (UIC0ER, 0x00000000); /* disable all */
145 mtdcr (UIC0CR, 0x00000000); /* all non-critical */
146 mtdcr (UIC0PR, 0xfc000000); /* */
147 mtdcr (UIC0TR, 0x00000000); /* */
148 mtdcr (UIC0VR, 0x00000001); /* */
150 /* Enable two GPIO 10~11 and TraceA signal */
151 mfsdr(SDR0_PFC0,reg);
153 mtsdr(SDR0_PFC0,reg);
155 mfsdr(SDR0_PFC1,reg);
157 mtsdr(SDR0_PFC1,reg);
159 /* Set GPIO 10 and 11 as output */
160 GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
161 GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
162 GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
164 *GpioOdr &= ~(0x00300000);
165 *GpioTcr |= 0x00300000;
166 *GpioOr |= 0x00300000;
171 int misc_init_r(void)
178 int checkboard (void)
181 int i = getenv_f("serial#", buf, sizeof(buf));
183 printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
190 #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
197 int board_eth_init(bd_t *bis)
200 return pci_eth_init(bis);