3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
29 int board_early_init_f(void)
33 /*--------------------------------------------------------------------
34 * Setup the external bus controller/chip selects
35 *-------------------------------------------------------------------*/
36 mtdcr(ebccfga, xbcfg);
38 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
40 mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41 mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
43 mtebc(pb1ap, 0x00000000);
44 mtebc(pb1cr, 0x00000000);
46 mtebc(pb2ap, 0x04814500);
47 /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
49 mtebc(pb3ap, 0x00000000);
50 mtebc(pb3cr, 0x00000000);
52 mtebc(pb4ap, 0x00000000);
53 mtebc(pb4cr, 0x00000000);
55 mtebc(pb5ap, 0x00000000);
56 mtebc(pb5cr, 0x00000000);
58 /*--------------------------------------------------------------------
60 *-------------------------------------------------------------------*/
62 /*setup Address lines for flash sizes larger than 16Meg. */
63 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
64 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
65 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
68 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
69 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
70 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
71 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
72 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
75 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
76 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
77 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
79 /* external interrupts IRQ0...3 */
80 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
81 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
82 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
85 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
86 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
87 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
88 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
89 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
91 /*--------------------------------------------------------------------
92 * Setup the interrupt controller polarities, triggers, etc.
93 *-------------------------------------------------------------------*/
94 mtdcr(uic0sr, 0xffffffff); /* clear all */
95 mtdcr(uic0er, 0x00000000); /* disable all */
96 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
97 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
98 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
99 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
100 mtdcr(uic0sr, 0xffffffff); /* clear all */
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
106 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
107 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
110 /*--------------------------------------------------------------------
111 * Setup other serial configuration
112 *-------------------------------------------------------------------*/
113 mfsdr(sdr_pci0, reg);
114 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
115 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
116 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
118 /*clear tmrclk divisor */
119 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
122 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
124 /*enable usb 1.1 fs device and remove usb 2.0 reset */
125 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
127 /*get rid of flash write protect */
128 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
133 int misc_init_r (void)
135 DECLARE_GLOBAL_DATA_PTR;
139 /* Re-do sizing to get full correct info */
140 mtdcr(ebccfga, pb0cr);
141 pbcr = mfdcr(ebccfgd);
142 switch (gd->bd->bi_flashsize) {
168 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
169 mtdcr(ebccfga, pb0cr);
170 mtdcr(ebccfgd, pbcr);
172 /* adjust flash start and offset */
173 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
174 gd->bd->bi_flashoffset = 0;
176 /* Monitor protection ON by default */
177 (void)flash_protect(FLAG_PROTECT_SET,
187 char *s = getenv("serial#");
189 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
199 /*************************************************************************
200 * sdram_init -- doesn't use serial presence detect.
202 * Assumes: 256 MB, ECC, non-registered
205 ************************************************************************/
206 void sdram_init(void)
210 /*--------------------------------------------------------------------
212 *------------------------------------------------------------------*/
213 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
214 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
215 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
216 mtsdram(mem_clktr, 0x40000000); /* ?? */
217 mtsdram(mem_wddctr, 0x40000000); /* ?? */
219 /*clear this first, if the DDR is enabled by a debugger
220 then you can not make changes. */
221 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
223 /*--------------------------------------------------------------------
224 * Setup for board-specific specific mem
225 *------------------------------------------------------------------*/
227 * Following for CAS Latency = 2.5 @ 133 MHz PLB
229 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
230 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
232 mtsdram(mem_tr0, 0x410a4012); /* ?? */
233 mtsdram(mem_tr1, 0x8080080b); /* ?? */
234 mtsdram(mem_rtr, 0x04080000); /* ?? */
235 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
236 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
237 udelay(400); /* Delay 200 usecs (min) */
239 /*--------------------------------------------------------------------
240 * Enable the controller, then wait for DCEN to complete
241 *------------------------------------------------------------------*/
242 mtsdram(mem_cfg0, 0x84000000); /* Enable */
245 mfsdram(mem_mcsts, reg);
246 if (reg & 0x80000000)
251 /*************************************************************************
254 ************************************************************************/
255 long int initdram(int board)
258 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
261 #if defined(CFG_DRAM_TEST)
264 unsigned long *mem = (unsigned long *)0;
265 const unsigned long kend = (1024 / sizeof(unsigned long));
270 for (k = 0; k < CFG_KBYTES_SDRAM;
271 ++k, mem += (1024 / sizeof(unsigned long))) {
272 if ((k & 1023) == 0) {
273 printf("%3d MB\r", k / 1024);
276 memset(mem, 0xaaaaaaaa, 1024);
277 for (n = 0; n < kend; ++n) {
278 if (mem[n] != 0xaaaaaaaa) {
279 printf("SDRAM test fails at: %08x\n",
285 memset(mem, 0x55555555, 1024);
286 for (n = 0; n < kend; ++n) {
287 if (mem[n] != 0x55555555) {
288 printf("SDRAM test fails at: %08x\n",
294 printf("SDRAM test passes\n");
299 /*************************************************************************
302 * This routine is called just prior to registering the hose and gives
303 * the board the opportunity to check things. Returning a value of zero
304 * indicates that things are bad & PCI initialization should be aborted.
306 * Different boards may wish to customize the pci controller structure
307 * (add regions, override default access routines, etc) or perform
308 * certain pre-initialization actions.
310 ************************************************************************/
311 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
312 int pci_pre_init(struct pci_controller *hose)
317 /*--------------------------------------------------------------------------+
318 * Bamboo is always configured as the host & requires the
319 * PCI arbiter to be enabled.
320 *--------------------------------------------------------------------------*/
321 mfsdr(sdr_sdstp1, strap);
322 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
323 printf("PCI: SDR0_STRP1[PAE] not set.\n");
324 printf("PCI: Configuration aborted.\n");
328 /*-------------------------------------------------------------------------+
329 | Set priority for all PLB3 devices to 0.
330 | Set PLB3 arbiter to fair mode.
331 +-------------------------------------------------------------------------*/
332 mfsdr(sdr_amp1, addr);
333 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
334 addr = mfdcr(plb3_acr);
335 mtdcr(plb3_acr, addr | 0x80000000);
337 /*-------------------------------------------------------------------------+
338 | Set priority for all PLB4 devices to 0.
339 +-------------------------------------------------------------------------*/
340 mfsdr(sdr_amp0, addr);
341 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
342 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
343 mtdcr(plb4_acr, addr);
345 /*-------------------------------------------------------------------------+
346 | Set Nebula PLB4 arbiter to fair mode.
347 +-------------------------------------------------------------------------*/
349 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
350 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
351 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
352 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
353 mtdcr(plb0_acr, addr);
356 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
357 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
358 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
359 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
360 mtdcr(plb1_acr, addr);
364 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
366 /*************************************************************************
369 * The bootstrap configuration provides default settings for the pci
370 * inbound map (PIM). But the bootstrap config choices are limited and
371 * may not be sufficient for a given board.
373 ************************************************************************/
374 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
375 void pci_target_init(struct pci_controller *hose)
377 /*--------------------------------------------------------------------------+
378 * Set up Direct MMIO registers
379 *--------------------------------------------------------------------------*/
380 /*--------------------------------------------------------------------------+
381 | PowerPC440 EP PCI Master configuration.
382 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
383 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
384 | Use byte reversed out routines to handle endianess.
385 | Make this region non-prefetchable.
386 +--------------------------------------------------------------------------*/
387 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
388 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
389 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
390 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
391 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
393 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
394 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
395 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
396 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
397 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
399 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
400 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
401 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
402 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
404 /*--------------------------------------------------------------------------+
405 * Set up Configuration registers
406 *--------------------------------------------------------------------------*/
408 /* Program the board's subsystem id/vendor id */
409 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
410 CFG_PCI_SUBSYS_VENDORID);
411 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
413 /* Configure command register as bus master */
414 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
416 /* 240nS PCI clock */
417 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
419 /* No error reporting */
420 pci_write_config_word(0, PCI_ERREN, 0);
422 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
425 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
427 /*************************************************************************
430 ************************************************************************/
431 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
432 void pci_master_init(struct pci_controller *hose)
434 unsigned short temp_short;
436 /*--------------------------------------------------------------------------+
437 | Write the PowerPC440 EP PCI Configuration regs.
438 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
439 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
440 +--------------------------------------------------------------------------*/
441 pci_read_config_word(0, PCI_COMMAND, &temp_short);
442 pci_write_config_word(0, PCI_COMMAND,
443 temp_short | PCI_COMMAND_MASTER |
446 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
448 /*************************************************************************
451 * This routine is called to determine if a pci scan should be
452 * performed. With various hardware environments (especially cPCI and
453 * PPMC) it's insufficient to depend on the state of the arbiter enable
454 * bit in the strap register, or generic host/adapter assumptions.
456 * Rather than hard-code a bad assumption in the general 440 code, the
457 * 440 pci code requires the board to decide at runtime.
459 * Return 0 for adapter mode, non-zero for host (monarch) mode.
462 ************************************************************************/
463 #if defined(CONFIG_PCI)
464 int is_pci_host(struct pci_controller *hose)
466 /* Bamboo is always configured as host. */
469 #endif /* defined(CONFIG_PCI) */
471 /*************************************************************************
474 * This routine is called to reset (keep alive) the watchdog timer
476 ************************************************************************/
477 #if defined(CONFIG_HW_WATCHDOG)
478 void hw_watchdog_reset(void)