git.sur5r.net Git - u-boot/blob - board/amcc/yucca/yucca.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24  *
  25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26  */
  27
  28 #include <common.h>
  29 #include <ppc4xx.h>
  30 #include <i2c.h>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33 #include <asm/4xx_pcie.h>
  34
  35 #include "yucca.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #undef PCIE_ENDPOINT
  40 /* #define PCIE_ENDPOINT 1 */
  41
  42 void fpga_init (void);
  43
  44 void get_sys_info(PPC440_SYS_INFO *board_cfg );
  45 int compare_to_true(char *str );
  46 char *remove_l_w_space(char *in_str );
  47 char *remove_t_w_space(char *in_str );
  48 int get_console_port(void);
  49
  50 #define DEBUG_ENV
  51 #ifdef DEBUG_ENV
  52 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  53 #else
  54 #define DEBUGF(fmt,args...)
  55 #endif
  56
  57 #define FALSE   0
  58 #define TRUE    1
  59
  60 int board_early_init_f (void)
  61 {
  62 /*----------------------------------------------------------------------------+
  63 | Define Boot devices
  64 +----------------------------------------------------------------------------*/
  65 #define BOOT_FROM_SMALL_FLASH           0x00
  66 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
  67 #define BOOT_FROM_PCI                   0x02
  68 #define BOOT_DEVICE_UNKNOWN             0x03
  69
  70 /*----------------------------------------------------------------------------+
  71 | EBC Devices Characteristics
  72 |   Peripheral Bank Access Parameters       -   EBC_BxAP
  73 |   Peripheral Bank Configuration Register  -   EBC_BxCR
  74 +----------------------------------------------------------------------------*/
  75
  76 /*
  77  * Small Flash and FRAM
  78  * BU Value
  79  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  80  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
  81  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
  82  */
  83 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
  84                                         EBC_BXAP_TWT_ENCODE(7)  | \
  85                                         EBC_BXAP_BCE_DISABLE    | \
  86                                         EBC_BXAP_BCT_2TRANS     | \
  87                                         EBC_BXAP_CSN_ENCODE(0)  | \
  88                                         EBC_BXAP_OEN_ENCODE(0)  | \
  89                                         EBC_BXAP_WBN_ENCODE(0)  | \
  90                                         EBC_BXAP_WBF_ENCODE(0)  | \
  91                                         EBC_BXAP_TH_ENCODE(0)   | \
  92                                         EBC_BXAP_RE_DISABLED    | \
  93                                         EBC_BXAP_SOR_DELAYED    | \
  94                                         EBC_BXAP_BEM_WRITEONLY  | \
  95                                         EBC_BXAP_PEN_DISABLED
  96
  97 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  98                                         EBC_BXCR_BS_16MB                | \
  99                                         EBC_BXCR_BU_RW                  | \
 100                                         EBC_BXCR_BW_8BIT
 101
 102 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
 103                                         EBC_BXCR_BS_16MB                | \
 104                                         EBC_BXCR_BU_RW                  | \
 105                                         EBC_BXCR_BW_8BIT
 106
 107 /*
 108  * Large Flash and SRAM
 109  * BU Value
 110  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 111  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 112  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
 113 */
 114 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
 115                                         EBC_BXAP_TWT_ENCODE(7)  | \
 116                                         EBC_BXAP_BCE_DISABLE    | \
 117                                         EBC_BXAP_BCT_2TRANS     | \
 118                                         EBC_BXAP_CSN_ENCODE(0)  | \
 119                                         EBC_BXAP_OEN_ENCODE(0)  | \
 120                                         EBC_BXAP_WBN_ENCODE(0)  | \
 121                                         EBC_BXAP_WBF_ENCODE(0)  | \
 122                                         EBC_BXAP_TH_ENCODE(0)   | \
 123                                         EBC_BXAP_RE_DISABLED    | \
 124                                         EBC_BXAP_SOR_DELAYED    | \
 125                                         EBC_BXAP_BEM_WRITEONLY  | \
 126                                         EBC_BXAP_PEN_DISABLED
 127
 128 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
 129                                         EBC_BXCR_BS_16MB                | \
 130                                         EBC_BXCR_BU_RW                  | \
 131                                         EBC_BXCR_BW_16BIT
 132
 133 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
 134                                         EBC_BXCR_BS_16MB                | \
 135                                         EBC_BXCR_BU_RW                  | \
 136                                         EBC_BXCR_BW_16BIT
 137
 138 /*
 139  * FPGA
 140  * BU value :
 141  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 142  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 143  */
 144 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
 145                                         EBC_BXAP_TWT_ENCODE(11) | \
 146                                         EBC_BXAP_BCE_DISABLE    | \
 147                                         EBC_BXAP_BCT_2TRANS     | \
 148                                         EBC_BXAP_CSN_ENCODE(10) | \
 149                                         EBC_BXAP_OEN_ENCODE(1)  | \
 150                                         EBC_BXAP_WBN_ENCODE(1)  | \
 151                                         EBC_BXAP_WBF_ENCODE(1)  | \
 152                                         EBC_BXAP_TH_ENCODE(1)   | \
 153                                         EBC_BXAP_RE_DISABLED    | \
 154                                         EBC_BXAP_SOR_DELAYED    | \
 155                                         EBC_BXAP_BEM_RW         | \
 156                                         EBC_BXAP_PEN_DISABLED
 157
 158 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
 159                                         EBC_BXCR_BS_1MB                 | \
 160                                         EBC_BXCR_BU_RW                  | \
 161                                         EBC_BXCR_BW_16BIT
 162
 163          unsigned long mfr;
 164         /*
 165          * Define Variables for EBC initialization depending on BOOTSTRAP option
 166          */
 167         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
 168         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
 169         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
 170
 171         /*-------------------------------------------------------------------+
 172          | Initialize EBC CONFIG -
 173          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 174          | default value :
 175          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 176          |
 177          +-------------------------------------------------------------------*/
 178         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
 179                         EBC_CFG_PTD_ENABLE |
 180                         EBC_CFG_RTC_16PERCLK |
 181                         EBC_CFG_ATC_PREVIOUS |
 182                         EBC_CFG_DTC_PREVIOUS |
 183                         EBC_CFG_CTC_PREVIOUS |
 184                         EBC_CFG_OEO_PREVIOUS |
 185                         EBC_CFG_EMC_DEFAULT |
 186                         EBC_CFG_PME_DISABLE |
 187                         EBC_CFG_PR_16);
 188
 189         /*-------------------------------------------------------------------+
 190          |
 191          |  PART 1 : Initialize EBC Bank 1
 192          |  ==============================
 193          | Bank1 is always associated to the EPLD.
 194          | It has to be initialized prior to other banks settings computation
 195          | since some board registers values may be needed to determine the
 196          | boot type
 197          |
 198          +-------------------------------------------------------------------*/
 199         mtebc(pb1ap, EBC_BXAP_FPGA);
 200         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
 201
 202         /*-------------------------------------------------------------------+
 203          |
 204          |  PART 2 : Determine which boot device was selected
 205          |  =================================================
 206          |
 207          |  Read Pin Strap Register in PPC440SPe
 208          |  Result can either be :
 209          |   - Boot strap = boot from EBC 8bits     => Small Flash
 210          |   - Boot strap = boot from PCI
 211          |   - Boot strap = IIC
 212          |  In case of boot from IIC, read Serial Device Strap Register1
 213          |
 214          |  Result can either be :
 215          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
 216          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
 217          |   - Boot from PCI
 218          |
 219          +-------------------------------------------------------------------*/
 220         /* Read Pin Strap Register in PPC440SP */
 221         mfsdr(SDR0_PINSTP, sdr0_pinstp);
 222         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 223
 224         switch (bootstrap_settings) {
 225                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
 226                         /*
 227                          * Strapping Option A
 228                          * Boot from EBC - 8 bits , Small Flash
 229                          */
 230                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 231                         break;
 232                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
 233                         /*
 234                          * Strappping Option B
 235                          * Boot from PCI
 236                          */
 237                         computed_boot_device = BOOT_FROM_PCI;
 238                         break;
 239                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
 240                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
 241                         /*
 242                          * Strapping Option C or D
 243                          * Boot Settings in IIC EEprom address 0x50 or 0x54
 244                          * Read Serial Device Strap Register1 in PPC440SPe
 245                          */
 246                         mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
 247                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 248                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 249
 250                         switch (boot_selection) {
 251                                 case SDR0_SDSTP1_ERPN_EBC:
 252                                         switch (ebc_data_width) {
 253                                                 case SDR0_SDSTP1_EBCW_16_BITS:
 254                                                         computed_boot_device =
 255                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
 256                                                         break;
 257                                                 case SDR0_SDSTP1_EBCW_8_BITS :
 258                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 259                                                         break;
 260                                         }
 261                                         break;
 262
 263                                 case SDR0_SDSTP1_ERPN_PCI:
 264                                         computed_boot_device = BOOT_FROM_PCI;
 265                                         break;
 266                                 default:
 267                                         /* should not occure */
 268                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 269                         }
 270                         break;
 271                 default:
 272                         /* should not be */
 273                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 274                         break;
 275         }
 276
 277         /*-------------------------------------------------------------------+
 278          |
 279          |  PART 3 : Compute EBC settings depending on selected boot device
 280          |  ======   ======================================================
 281          |
 282          | Resulting EBC init will be among following configurations :
 283          |
 284          |  - Boot from EBC 8bits => boot from Small Flash selected
 285          |            EBC-CS0     = Small Flash
 286          |            EBC-CS2     = Large Flash and SRAM
 287          |
 288          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
 289          |            EBC-CS0     = Large Flash or SRAM
 290          |            EBC-CS2     = Small Flash
 291          |
 292          |  - Boot from PCI
 293          |            EBC-CS0     = not initialized to avoid address contention
 294          |            EBC-CS2     = same as boot from Small Flash selected
 295          |
 296          +-------------------------------------------------------------------*/
 297         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
 298         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
 299
 300         switch (computed_boot_device) {
 301                 /*-------------------------------------------------------------------*/
 302                 case BOOT_FROM_PCI:
 303                 /*-------------------------------------------------------------------*/
 304                         /*
 305                          * By Default CS2 is affected to LARGE Flash
 306                          * do not initialize SMALL FLASH to avoid address contention
 307                          * Large Flash
 308                          */
 309                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
 310                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 311                         break;
 312
 313                 /*-------------------------------------------------------------------*/
 314                 case BOOT_FROM_SMALL_FLASH:
 315                 /*-------------------------------------------------------------------*/
 316                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
 317                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
 318
 319                         /*
 320                          * Large Flash or SRAM
 321                          */
 322                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
 323                         ebc0_cs2_bxap_value = 0x048ff240;
 324                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 325                         break;
 326
 327                 /*-------------------------------------------------------------------*/
 328                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 329                 /*-------------------------------------------------------------------*/
 330                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
 331                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
 332
 333                         /* Small flash */
 334                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
 335                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
 336                         break;
 337
 338                 /*-------------------------------------------------------------------*/
 339                 default:
 340                 /*-------------------------------------------------------------------*/
 341                         /* BOOT_DEVICE_UNKNOWN */
 342                         break;
 343         }
 344
 345         mtebc(pb0ap, ebc0_cs0_bxap_value);
 346         mtebc(pb0cr, ebc0_cs0_bxcr_value);
 347         mtebc(pb2ap, ebc0_cs2_bxap_value);
 348         mtebc(pb2cr, ebc0_cs2_bxcr_value);
 349
 350         /*--------------------------------------------------------------------+
 351          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
 352          +--------------------------------------------------------------------+
 353         +---------------------------------------------------------------------+
 354         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
 355         +---------+-----------------------------------+-------+-------+-------+
 356         | IRQ 00  | UART0                             | High  | Level | Non   |
 357         | IRQ 01  | UART1                             | High  | Level | Non   |
 358         | IRQ 02  | IIC0                              | High  | Level | Non   |
 359         | IRQ 03  | IIC1                              | High  | Level | Non   |
 360         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
 361         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
 362         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
 363         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
 364         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
 365         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
 366         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
 367         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
 368         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
 369         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
 370         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
 371         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
 372         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
 373         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
 374         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
 375         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
 376         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
 377         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
 378         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
 379         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
 380         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
 381         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
 382         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
 383         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
 384         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
 385         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
 386         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
 387         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
 388         |----------------------------------------------------------------------
 389         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
 390         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
 391         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
 392         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
 393         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
 394         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
 395         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
 396         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
 397         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
 398         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
 399         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
 400         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
 401         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
 402         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
 403         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
 404         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 405         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 406         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
 407         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 408         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 409         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 410         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 411         | IRQ 54  | DMA Error                         | High  | Level | Non   |
 412         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
 413         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
 414         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
 415         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 416         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 417         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
 418         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
 419         | IRQ 62  | Reserved                          | High  | Level | Non   |
 420         | IRQ 63  | XOR                               | High  | Level | Non   |
 421         |----------------------------------------------------------------------
 422         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 423         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 424         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 425         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 426         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 427         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 428         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 429         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 430         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 431         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 432         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 433         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 434         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 435         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 436         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 437         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 438         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 439         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 440         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 441         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 442         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 443         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 444         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 445         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 446         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 447         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 448         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 449         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 450         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 451         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 452         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 453         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 454         |---------------------------------------------------------------------
 455         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
 456         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
 457         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
 458         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
 459         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
 460         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
 461         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
 462         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
 463         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
 464         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
 465         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
 466         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
 467         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 468         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 469         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 470         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 471         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 472         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 473         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 474         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 475         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 476         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 477         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 478         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 479         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 480         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 481         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 482         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 483         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 484         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 485         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 486         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 487         +---------+-----------------------------------+-------+-------+------*/
 488         /*--------------------------------------------------------------------+
 489          | Put UICs in PowerPC440SPemode.
 490          | Initialise UIC registers.  Clear all interrupts.  Disable all
 491          | interrupts.
 492          | Set critical interrupt values.  Set interrupt polarities.  Set
 493          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 494          | interrupts again.
 495          +-------------------------------------------------------------------*/
 496         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
 497         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
 498         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
 499                                          * interrupts */
 500         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
 501         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
 502         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 503                                          * priority */
 504         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
 505         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
 506
 507         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 508         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
 509         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
 510                                          * interrupts */
 511         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
 512         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
 513         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 514                                          * priority */
 515         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 516         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 517
 518         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
 519         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
 520         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
 521                                          * interrupts */
 522         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
 523         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
 524         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 525                                          * priority */
 526         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
 527         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
 528
 529         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 530         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
 531                                          * cascade to be checked */
 532         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
 533                                          * interrupts */
 534         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
 535         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
 536         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 537                                          * priority */
 538         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
 539         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 540
 541         /* SDR0_MFR should be part of Ethernet init */
 542         mfsdr (sdr_mfr, mfr);
 543         mfr &= ~SDR0_MFR_ECS_MASK;
 544         /*mtsdr(sdr_mfr, mfr);*/
 545         fpga_init();
 546
 547         return 0;
 548 }
 549
 550 int checkboard (void)
 551 {
 552         char *s = getenv("serial#");
 553
 554         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
 555         if (s != NULL) {
 556                 puts(", serial# ");
 557                 puts(s);
 558         }
 559         putc('\n');
 560
 561         return 0;
 562 }
 563
 564 /*
 565  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 566  * board specific values.
 567  */
 568 static int ppc440spe_rev_a(void)
 569 {
 570         if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
 571                 return 1;
 572         else
 573                 return 0;
 574 }
 575
 576 u32 ddr_wrdtr(u32 default_val) {
 577         /*
 578          * Yucca boards with 440SPe rev. A need a slightly different setup
 579          * for the MCIF0_WRDTR register.
 580          */
 581         if (ppc440spe_rev_a())
 582                 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
 583
 584         return default_val;
 585 }
 586
 587 u32 ddr_clktr(u32 default_val) {
 588         /*
 589          * Yucca boards with 440SPe rev. A need a slightly different setup
 590          * for the MCIF0_CLKTR register.
 591          */
 592         if (ppc440spe_rev_a())
 593                 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
 594
 595         return default_val;
 596 }
 597
 598 #if defined(CFG_DRAM_TEST)
 599 int testdram (void)
 600 {
 601         uint *pstart = (uint *) 0x00000000;
 602         uint *pend = (uint *) 0x08000000;
 603         uint *p;
 604
 605         for (p = pstart; p < pend; p++)
 606                 *p = 0xaaaaaaaa;
 607
 608         for (p = pstart; p < pend; p++) {
 609                 if (*p != 0xaaaaaaaa) {
 610                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 611                         return 1;
 612                 }
 613         }
 614
 615         for (p = pstart; p < pend; p++)
 616                 *p = 0x55555555;
 617
 618         for (p = pstart; p < pend; p++) {
 619                 if (*p != 0x55555555) {
 620                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 621                         return 1;
 622                 }
 623         }
 624         return 0;
 625 }
 626 #endif
 627
 628 /*************************************************************************
 629  *  pci_pre_init
 630  *
 631  *  This routine is called just prior to registering the hose and gives
 632  *  the board the opportunity to check things. Returning a value of zero
 633  *  indicates that things are bad & PCI initialization should be aborted.
 634  *
 635  *      Different boards may wish to customize the pci controller structure
 636  *      (add regions, override default access routines, etc) or perform
 637  *      certain pre-initialization actions.
 638  *
 639  ************************************************************************/
 640 #if defined(CONFIG_PCI)
 641 int pci_pre_init(struct pci_controller * hose )
 642 {
 643         unsigned long strap;
 644
 645         /*-------------------------------------------------------------------+
 646          *      The yucca board is always configured as the host & requires the
 647          *      PCI arbiter to be enabled.
 648          *-------------------------------------------------------------------*/
 649         mfsdr(sdr_sdstp1, strap);
 650         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 651                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 652                 return 0;
 653         }
 654
 655         return 1;
 656 }
 657 #endif  /* defined(CONFIG_PCI) */
 658
 659 /*************************************************************************
 660  *  pci_target_init
 661  *
 662  *      The bootstrap configuration provides default settings for the pci
 663  *      inbound map (PIM). But the bootstrap config choices are limited and
 664  *      may not be sufficient for a given board.
 665  *
 666  ************************************************************************/
 667 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 668 void pci_target_init(struct pci_controller * hose )
 669 {
 670         /*-------------------------------------------------------------------+
 671          * Disable everything
 672          *-------------------------------------------------------------------*/
 673         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 674         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 675         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 676         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 677
 678         /*-------------------------------------------------------------------+
 679          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 680          * strapping options to not support sizes such as 128/256 MB.
 681          *-------------------------------------------------------------------*/
 682         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 683         out32r( PCIX0_PIM0LAH, 0 );
 684         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 685         out32r( PCIX0_BAR0, 0 );
 686
 687         /*-------------------------------------------------------------------+
 688          * Program the board's subsystem id/vendor id
 689          *-------------------------------------------------------------------*/
 690         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 691         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 692
 693         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 694 }
 695 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 696
 697 #if defined(CONFIG_PCI)
 698 /*************************************************************************
 699  *  is_pci_host
 700  *
 701  *      This routine is called to determine if a pci scan should be
 702  *      performed. With various hardware environments (especially cPCI and
 703  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 704  *      bit in the strap register, or generic host/adapter assumptions.
 705  *
 706  *      Rather than hard-code a bad assumption in the general 440 code, the
 707  *      440 pci code requires the board to decide at runtime.
 708  *
 709  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 710  *
 711  *
 712  ************************************************************************/
 713 int is_pci_host(struct pci_controller *hose)
 714 {
 715         /* The yucca board is always configured as host. */
 716         return 1;
 717 }
 718
 719 int yucca_pcie_card_present(int port)
 720 {
 721         u16 reg;
 722
 723         reg = in_be16((u16 *)FPGA_REG1C);
 724         switch(port) {
 725         case 0:
 726                 return !(reg & FPGA_REG1C_PE0_PRSNT);
 727         case 1:
 728                 return !(reg & FPGA_REG1C_PE1_PRSNT);
 729         case 2:
 730                 return !(reg & FPGA_REG1C_PE2_PRSNT);
 731         default:
 732                 return 0;
 733         }
 734 }
 735
 736 /*
 737  * For the given slot, set rootpoint mode, send power to the slot,
 738  * turn on the green LED and turn off the yellow LED, enable the clock
 739  * and turn off reset.
 740  */
 741 void yucca_setup_pcie_fpga_rootpoint(int port)
 742 {
 743         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 744
 745         switch(port) {
 746         case 0:
 747                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 748                 endpoint    = 0;
 749                 power       = FPGA_REG1A_PE0_PWRON;
 750                 green_led   = FPGA_REG1A_PE0_GLED;
 751                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 752                 yellow_led  = FPGA_REG1A_PE0_YLED;
 753                 reset_off   = FPGA_REG1C_PE0_PERST;
 754                 break;
 755         case 1:
 756                 rootpoint   = 0;
 757                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 758                 power       = FPGA_REG1A_PE1_PWRON;
 759                 green_led   = FPGA_REG1A_PE1_GLED;
 760                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 761                 yellow_led  = FPGA_REG1A_PE1_YLED;
 762                 reset_off   = FPGA_REG1C_PE1_PERST;
 763                 break;
 764         case 2:
 765                 rootpoint   = 0;
 766                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 767                 power       = FPGA_REG1A_PE2_PWRON;
 768                 green_led   = FPGA_REG1A_PE2_GLED;
 769                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 770                 yellow_led  = FPGA_REG1A_PE2_YLED;
 771                 reset_off   = FPGA_REG1C_PE2_PERST;
 772                 break;
 773
 774         default:
 775                 return;
 776         }
 777
 778         out_be16((u16 *)FPGA_REG1A,
 779                  ~(power | clock | green_led) &
 780                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 781
 782         out_be16((u16 *)FPGA_REG1C,
 783                  ~(endpoint | reset_off) &
 784                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
 785         /*
 786          * Leave device in reset for a while after powering on the
 787          * slot to give it a chance to initialize.
 788          */
 789         udelay(250 * 1000);
 790
 791         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
 792 }
 793 /*
 794  * For the given slot, set endpoint mode, send power to the slot,
 795  * turn on the green LED and turn off the yellow LED, enable the clock
 796  * .In end point mode reset bit is  read only.
 797  */
 798 void yucca_setup_pcie_fpga_endpoint(int port)
 799 {
 800         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 801
 802         switch(port) {
 803         case 0:
 804                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 805                 endpoint    = 0;
 806                 power       = FPGA_REG1A_PE0_PWRON;
 807                 green_led   = FPGA_REG1A_PE0_GLED;
 808                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 809                 yellow_led  = FPGA_REG1A_PE0_YLED;
 810                 reset_off   = FPGA_REG1C_PE0_PERST;
 811                 break;
 812         case 1:
 813                 rootpoint   = 0;
 814                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 815                 power       = FPGA_REG1A_PE1_PWRON;
 816                 green_led   = FPGA_REG1A_PE1_GLED;
 817                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 818                 yellow_led  = FPGA_REG1A_PE1_YLED;
 819                 reset_off   = FPGA_REG1C_PE1_PERST;
 820                 break;
 821         case 2:
 822                 rootpoint   = 0;
 823                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 824                 power       = FPGA_REG1A_PE2_PWRON;
 825                 green_led   = FPGA_REG1A_PE2_GLED;
 826                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 827                 yellow_led  = FPGA_REG1A_PE2_YLED;
 828                 reset_off   = FPGA_REG1C_PE2_PERST;
 829                 break;
 830
 831         default:
 832                 return;
 833         }
 834
 835         out_be16((u16 *)FPGA_REG1A,
 836                  ~(power | clock | green_led) &
 837                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 838
 839         out_be16((u16 *)FPGA_REG1C,
 840                  ~(rootpoint | reset_off) &
 841                  (endpoint | in_be16((u16 *)FPGA_REG1C)));
 842 }
 843
 844 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 845
 846 void pcie_setup_hoses(int busno)
 847 {
 848         struct pci_controller *hose;
 849         int i, bus;
 850         char *env;
 851         unsigned int delay;
 852
 853         /*
 854          * assume we're called after the PCIX hose is initialized, which takes
 855          * bus ID 0 and therefore start numbering PCIe's from 1.
 856          */
 857         bus = busno;
 858         for (i = 0; i <= 2; i++) {
 859                 /* Check for yucca card presence */
 860                 if (!yucca_pcie_card_present(i))
 861                         continue;
 862
 863 #ifdef PCIE_ENDPOINT
 864                 yucca_setup_pcie_fpga_endpoint(i);
 865                 if (ppc4xx_init_pcie_endport(i)) {
 866 #else
 867                 yucca_setup_pcie_fpga_rootpoint(i);
 868                 if (ppc4xx_init_pcie_rootport(i)) {
 869 #endif
 870                         printf("PCIE%d: initialization failed\n", i);
 871                         continue;
 872                 }
 873
 874                 hose = &pcie_hose[i];
 875                 hose->first_busno = bus;
 876                 hose->last_busno = bus;
 877                 hose->current_busno = bus;
 878
 879                 /* setup mem resource */
 880                 pci_set_region(hose->regions + 0,
 881                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 882                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 883                         CFG_PCIE_MEMSIZE,
 884                         PCI_REGION_MEM
 885                         );
 886                 hose->region_count = 1;
 887                 pci_register_hose(hose);
 888
 889 #ifdef PCIE_ENDPOINT
 890                 ppc4xx_setup_pcie_endpoint(hose, i);
 891                 /*
 892                  * Reson for no scanning is endpoint can not generate
 893                  * upstream configuration accesses.
 894                  */
 895 #else
 896                 ppc4xx_setup_pcie_rootpoint(hose, i);
 897
 898                 env = getenv ("pciscandelay");
 899                 if (env != NULL) {
 900                         delay = simple_strtoul (env, NULL, 10);
 901                         if (delay > 5)
 902                                 printf ("Warning, expect noticable delay before PCIe"
 903                                         "scan due to 'pciscandelay' value!\n");
 904                         mdelay (delay * 1000);
 905                 }
 906
 907                 /*
 908                  * Config access can only go down stream
 909                  */
 910                 hose->last_busno = pci_hose_scan(hose);
 911                 bus = hose->last_busno + 1;
 912 #endif
 913         }
 914 }
 915 #endif  /* defined(CONFIG_PCI) */
 916
 917 int misc_init_f (void)
 918 {
 919         uint reg;
 920 #if defined(CONFIG_STRESS)
 921         uint i ;
 922         uint disp;
 923 #endif
 924
 925         out16(FPGA_REG10, (in16(FPGA_REG10) &
 926                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
 927                                 FPGA_REG10_10MHZ_ENABLE |
 928                                 FPGA_REG10_100MHZ_ENABLE |
 929                                 FPGA_REG10_GIGABIT_ENABLE |
 930                                 FPGA_REG10_FULL_DUPLEX );
 931
 932         udelay(10000);  /* wait 10ms */
 933
 934         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
 935
 936         /* minimal init for PCIe */
 937         /* pci express 0 Endpoint Mode */
 938         mfsdr(SDR0_PE0DLPSET, reg);
 939         reg &= (~0x00400000);
 940         mtsdr(SDR0_PE0DLPSET, reg);
 941         /* pci express 1 Rootpoint  Mode */
 942         mfsdr(SDR0_PE1DLPSET, reg);
 943         reg |= 0x00400000;
 944         mtsdr(SDR0_PE1DLPSET, reg);
 945         /* pci express 2 Rootpoint  Mode */
 946         mfsdr(SDR0_PE2DLPSET, reg);
 947         reg |= 0x00400000;
 948         mtsdr(SDR0_PE2DLPSET, reg);
 949
 950         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 951                                 ~FPGA_REG1C_PE0_ROOTPOINT &
 952                                 ~FPGA_REG1C_PE1_ENDPOINT  &
 953                                 ~FPGA_REG1C_PE2_ENDPOINT));
 954
 955 #if defined(CONFIG_STRESS)
 956         /*
 957          * all this setting done by linux only needed by stress an charac. test
 958          * procedure
 959          * PCIe 1 Rootpoint PCIe2 Endpoint
 960          * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 961          * Power Level
 962          */
 963         for (i = 0, disp = 0; i < 8; i++, disp += 3) {
 964                 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 965                 reg |= 0x33000000;
 966                 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 967         }
 968
 969         /*
 970          * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 971          * Power Level
 972          */
 973         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 974                 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 975                 reg |= 0x33000000;
 976                 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 977         }
 978
 979         /*
 980          * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 981          * Power Level
 982          */
 983         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 984                 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 985                 reg |= 0x33000000;
 986                 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 987         }
 988
 989         reg = 0x21242222;
 990         mtsdr(SDR0_PE2UTLSET1, reg);
 991         reg = 0x11000000;
 992         mtsdr(SDR0_PE2UTLSET2, reg);
 993         /* pci express 1 Endpoint  Mode */
 994         reg = 0x00004000;
 995         mtsdr(SDR0_PE2DLPSET, reg);
 996
 997         mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
 998 #endif
 999         return 0;
1000 }
1001
1002 void fpga_init(void)
1003 {
1004         /*
1005          * by default sdram access is disabled by fpga
1006          */
1007         out16(FPGA_REG10, (in16 (FPGA_REG10) |
1008                                 FPGA_REG10_SDRAM_ENABLE |
1009                                 FPGA_REG10_ENABLE_DISPLAY ));
1010
1011         return;
1012 }
1013
1014 #ifdef CONFIG_POST
1015 /*
1016  * Returns 1 if keys pressed to start the power-on long-running tests
1017  * Called from board_init_f().
1018  */
1019 int post_hotkeys_pressed(void)
1020 {
1021         return (ctrlc());
1022 }
1023 #endif
1024
1025 /*---------------------------------------------------------------------------+
1026  | onboard_pci_arbiter_selected => from EPLD
1027  +---------------------------------------------------------------------------*/
1028 int onboard_pci_arbiter_selected(int core_pci)
1029 {
1030 #if 0
1031         unsigned long onboard_pci_arbiter_sel;
1032
1033         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1034
1035         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1036                 return (BOARD_OPTION_SELECTED);
1037         else
1038 #endif
1039         return (BOARD_OPTION_NOT_SELECTED);
1040 }