2 * @file powerspan.h Header file for PowerSpan II code.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define CLEAR_MASTER_ABORT 0xdeadbeef
29 #define NO_DEVICE_FOUND -1
30 #define ILLEGAL_REG_OFFSET -2
34 #define REG_P1_CSR 0x004
35 #define REGS_P1_BST 0x018
36 #define REG_P1_ERR_CSR 0x150
37 #define REG_P1_MISC_CSR 0x160
38 #define REGS_P1_TGT_CSR 0x100
39 #define REGS_P1_TGT_TADDR 0x104
40 #define REGS_PB_SLAVE_CSR 0x200
41 #define REGS_PB_SLAVE_TADDR 0x204
42 #define REGS_PB_SLAVE_BADDR 0x208
43 #define REG_CONFIG_ADDRESS 0x290
44 #define REG_CONFIG_DATA 0x294
45 #define REG_PB_ERR_CSR 0x2B0
46 #define REG_PB_MISC_CSR 0x2C0
47 #define REG_MISC_CSR 0x400
48 #define REG_I2C_CSR 0x408
49 #define REG_RESET_CSR 0x40C
50 #define REG_ISR0 0x410
51 #define REG_ISR1 0x414
52 #define REG_IER0 0x418
53 #define REG_MBOX_MAP 0x420
54 #define REG_HW_MAP 0x42C
57 #define CSR_MEMORY_SPACE_ENABLE 0x00000002
58 #define CSR_PCI_MASTER_ENABLE 0x00000004
60 #define P1_BST_OFF 0x04
62 #define PX_ERR_ERR_STATUS 0x01000000
64 #define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00
65 #define PX_MISC_CSR_MAX_RETRY 0x00000F00
66 #define PX_MISC_REG_BAR_ENABLE 0x00008000
67 #define PB_MISC_TEA_ENABLE 0x00000010
68 #define PB_MISC_MAC_TEA 0x00000040
70 #define P1_TGT_IMAGE_OFF 0x010
71 #define PX_TGT_CSR_IMG_EN 0x80000000
72 #define PX_TGT_CSR_TA_EN 0x40000000
73 #define PX_TGT_CSR_BAR_EN 0x20000000
74 #define PX_TGT_CSR_MD_EN 0x10000000
75 #define PX_TGT_CSR_MODE 0x00800000
76 #define PX_TGT_CSR_DEST 0x00400000
77 #define PX_TGT_CSR_MEM_IO 0x00200000
78 #define PX_TGT_CSR_GBL 0x00080000
79 #define PX_TGT_CSR_CL 0x00040000
80 #define PX_TGT_CSR_PRKEEP 0x00000080
82 #define PX_TGT_CSR_BS_MASK 0x0F000000
83 #define PX_TGT_MEM_IO 0x00200000
84 #define PX_TGT_CSR_RTT_MASK 0x001F0000
85 #define PX_TGT_CSR_RTT_READ 0x000A0000
86 #define PX_TGT_CSR_WTT_MASK 0x00001F00
87 #define PX_TGT_CSR_WTT_WFLUSH 0x00000200
88 #define PX_TGT_CSR_END_MASK 0x00000060
89 #define PX_TGT_CSR_BIG_END 0x00000040
90 #define PX_TGT_CSR_TRUE_LEND 0x00000060
91 #define PX_TGT_CSR_RDAMT_MASK 0x00000007
93 #define PX_TGT_CSR_BS_64MB 0xa
94 #define PX_TGT_CSR_BS_16MB 0x8
96 #define PX_TGT_USE_MEM_IO 1
97 #define PX_TGT_NOT_MEM_IO 0
99 #define PB_SLAVE_IMAGE_OFF 0x010
100 #define PB_SLAVE_CSR_IMG_EN 0x80000000
101 #define PB_SLAVE_CSR_TA_EN 0x40000000
102 #define PB_SLAVE_CSR_MD_EN 0x20000000
103 #define PB_SLAVE_CSR_MODE 0x00800000
104 #define PB_SLAVE_CSR_DEST 0x00400000
105 #define PB_SLAVE_CSR_MEM_IO 0x00200000
106 #define PB_SLAVE_CSR_PRKEEP 0x00000080
108 #define PB_SLAVE_CSR_BS_MASK 0x1F000000
109 #define PB_SLAVE_CSR_END_MASK 0x00000060
110 #define PB_SLAVE_CSR_BIG_END 0x00000040
111 #define PB_SLAVE_CSR_TRUE_LEND 0x00000060
112 #define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
114 #define PB_SLAVE_USE_MEM_IO 1
115 #define PB_SLAVE_NOT_MEM_IO 0
118 #define MISC_CSR_PCI1_LOCK 0x00000080
120 #define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */
121 #define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */
122 #define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */
123 #define I2C_CSR_CS 0x00000E00 /* Chip Select */
124 #define I2C_CSR_RW 0x00000100 /* Read/Write */
125 #define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */
126 #define I2C_CSR_ERR 0x00000040 /* Error */
128 #define I2C_EEPROM_DEV 0xa
129 #define I2C_EEPROM_CHIP_SEL 0
134 #define RESET_CSR_EEPROM_LOAD 0x00000010
136 #define ISR_CLEAR_ALL 0xFFFFFFFF
138 #define IER0_DMA_INTS_EN 0x0F000000
139 #define IER0_PCI_1_EN 0x00400000
140 #define IER0_HW_INTS_EN 0x003F0000
141 #define IER0_MB_INTS_EN 0x000000FF
142 #define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
144 #define MBOX_MAP_TO_INT4 0xCCCCCCCC
146 #define HW_MAP_HW4_TO_INT4 0x000C0000
148 #define IDR_PCI_A_OUT 0x40000000
149 #define IDR_MBOX_OUT 0x10000000
152 int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
153 int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
154 int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
155 int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
156 int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
157 int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
159 unsigned int PowerSpanRead(unsigned int theOffset);
160 void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
162 int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
164 int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
165 int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
167 int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
168 int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);