2 * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <generated/asm-offsets.h>
10 #include <asm/macro.h>
11 #include <asm/arch/imx-regs.h>
16 * setup AIPI1 and AIPI2
18 write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
19 write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
20 write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
21 write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
23 /* Change SDRAM signal strengh */
25 ldr r1, =ACFG_GPCR_VAL
34 /* disable MPLL/SPLL first */
36 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
40 * pll clock initialization predefined in apf27.h
42 write32 MPCTL0, ACFG_MPCTL0_VAL
43 write32 SPCTL0, ACFG_SPCTL0_VAL
45 write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
54 /* peripheral clock divider */
55 write32 PCDR0, ACFG_PCDR0_VAL
56 write32 PCDR1, ACFG_PCDR1_VAL
58 /* Configure PCCR0 and PCCR1 */
59 write32 PCCR0, ACFG_PCCR0_VAL
60 write32 PCCR1, ACFG_PCCR1_VAL
62 .endm /* init_clock */
65 /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
67 ldr r4, =ESDMISC_SDRAM_RDY
68 2: ldr r1, [r0, #ESDMISC_ROF]
72 /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
74 ldr r4, =ACFG_ESDMISC_VAL
75 orr r1, r4, #ESDMISC_MDDR_DL_RST
76 str r1, [r0, #ESDMISC_ROF]
78 /* Hold for more than 200ns */
86 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
87 str r1, [r0, #ESDCFG0_ROF]
90 ldr r1, =ACFG_PRECHARGE_CMD
91 str r1, [r0, #ESDCTL0_ROF]
93 /* write8(0xA0001000, any value) */
94 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
97 ldr r1, =ACFG_AUTOREFRESH_CMD
98 str r1, [r0, #ESDCTL0_ROF]
100 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
102 ldr r6,=0x7 /* load loop counter */
103 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
107 ldr r1, =ACFG_SET_MODE_REG_CMD
108 str r1, [r0, #ESDCTL0_ROF]
110 /* set standard mode register */
111 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
114 /* set extended mode register */
115 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
118 ldr r1, =ACFG_NORMAL_RW_CMD
119 str r1, [r0, #ESDCTL0_ROF]
122 ldr r0, =IMX_ESD_BASE
123 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
124 str r1, [r0, #ESDCFG1_ROF]
126 ldr r0, =IMX_ESD_BASE
127 ldr r1, =ACFG_PRECHARGE_CMD
128 str r1, [r0, #ESDCTL1_ROF]
130 /* write8(0xB0001000, any value) */
131 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
134 ldr r1, =ACFG_AUTOREFRESH_CMD
135 str r1, [r0, #ESDCTL1_ROF]
137 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
139 ldr r6,=0x7 /* load loop counter */
140 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
144 ldr r1, =ACFG_SET_MODE_REG_CMD
145 str r1, [r0, #ESDCTL1_ROF]
147 /* set standard mode register */
148 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
151 /* set extended mode register */
152 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
155 ldr r1, =ACFG_NORMAL_RW_CMD
156 str r1, [r0, #ESDCTL1_ROF]
164 #ifdef CONFIG_SPL_BUILD