2 * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <generated/asm-offsets.h>
10 #include <asm/arch/imx-regs.h>
15 * setup AIPI1 and AIPI2
17 write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
18 write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
19 write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
20 write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
22 /* Change SDRAM signal strengh */
24 ldr r1, =ACFG_GPCR_VAL
33 /* disable MPLL/SPLL first */
35 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
39 * pll clock initialization predefined in apf27.h
41 write32 MPCTL0, ACFG_MPCTL0_VAL
42 write32 SPCTL0, ACFG_SPCTL0_VAL
44 write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
53 /* peripheral clock divider */
54 write32 PCDR0, ACFG_PCDR0_VAL
55 write32 PCDR1, ACFG_PCDR1_VAL
57 /* Configure PCCR0 and PCCR1 */
58 write32 PCCR0, ACFG_PCCR0_VAL
59 write32 PCCR1, ACFG_PCCR1_VAL
61 .endm /* init_clock */
64 /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
66 ldr r4, =ESDMISC_SDRAM_RDY
67 2: ldr r1, [r0, #ESDMISC_ROF]
71 /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
73 ldr r4, =ACFG_ESDMISC_VAL
74 orr r1, r4, #ESDMISC_MDDR_DL_RST
75 str r1, [r0, #ESDMISC_ROF]
77 /* Hold for more than 200ns */
85 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
86 str r1, [r0, #ESDCFG0_ROF]
89 ldr r1, =ACFG_PRECHARGE_CMD
90 str r1, [r0, #ESDCTL0_ROF]
92 /* write8(0xA0001000, any value) */
93 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
96 ldr r1, =ACFG_AUTOREFRESH_CMD
97 str r1, [r0, #ESDCTL0_ROF]
99 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
101 ldr r6,=0x7 /* load loop counter */
102 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
106 ldr r1, =ACFG_SET_MODE_REG_CMD
107 str r1, [r0, #ESDCTL0_ROF]
109 /* set standard mode register */
110 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
113 /* set extended mode register */
114 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
117 ldr r1, =ACFG_NORMAL_RW_CMD
118 str r1, [r0, #ESDCTL0_ROF]
121 ldr r0, =IMX_ESD_BASE
122 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
123 str r1, [r0, #ESDCFG1_ROF]
125 ldr r0, =IMX_ESD_BASE
126 ldr r1, =ACFG_PRECHARGE_CMD
127 str r1, [r0, #ESDCTL1_ROF]
129 /* write8(0xB0001000, any value) */
130 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
133 ldr r1, =ACFG_AUTOREFRESH_CMD
134 str r1, [r0, #ESDCTL1_ROF]
136 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
138 ldr r6,=0x7 /* load loop counter */
139 1: str r5,[r4] /* run auto-refresh cycle to array 0 */
143 ldr r1, =ACFG_SET_MODE_REG_CMD
144 str r1, [r0, #ESDCTL1_ROF]
146 /* set standard mode register */
147 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
150 /* set extended mode register */
151 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
154 ldr r1, =ACFG_NORMAL_RW_CMD
155 str r1, [r0, #ESDCTL1_ROF]
163 #ifdef CONFIG_SPL_BUILD