1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
16 * Philippe Robin, <philippe.robin@arm.com>
22 #ifdef CONFIG_ARCH_CINTEGRATOR
23 #define DIV_CLOCK_INIT 1
24 #define TIMER_LOAD_VAL 0xFFFFFFFFL
26 #define DIV_CLOCK_INIT 256
27 #define TIMER_LOAD_VAL 0x0000FFFFL
29 /* The Integrator/CP timer1 is clocked at 1MHz
30 * can be divided by 16 or 256
31 * and can be set up as a 32-bit timer
33 /* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
34 /* Keep total timer count to avoid losing decrements < div_timer */
35 static unsigned long long total_count = 0;
36 static unsigned long long lastdec; /* Timer reading at last call */
37 /* Divisor applied to timer clock */
38 static unsigned long long div_clock = DIV_CLOCK_INIT;
39 static unsigned long long div_timer = 1; /* Divisor to convert timer reading
40 * change to U-Boot ticks
42 /* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
43 static ulong timestamp; /* U-Boot ticks since startup */
45 #define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
47 /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
48 * - unless otherwise stated
51 /* starts up a counter
52 * - the Integrator/CP timer can be set up to issue an interrupt */
55 /* Load timer with initial value */
56 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
57 #ifdef CONFIG_ARCH_CINTEGRATOR
63 * divider 1 00 == less rounding error
67 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
76 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
79 /* init the timestamp */
81 /* capure current decrementer value */
83 /* start "advancing" time stamp from 0 */
86 div_timer = CONFIG_SYS_HZ_CLOCK;
87 do_div(div_timer, CONFIG_SYS_HZ);
88 do_div(div_timer, div_clock);
94 * timer without interrupts
96 ulong get_timer (ulong base_ticks)
98 return get_timer_masked () - base_ticks;
101 /* delay usec useconds */
102 void __udelay (unsigned long usec)
106 /* Convert to U-Boot ticks */
107 tmo = usec * CONFIG_SYS_HZ;
110 tmp = get_timer_masked(); /* get current timestamp */
111 tmo += tmp; /* form target timestamp */
113 while (get_timer_masked () < tmo) {/* loop till event */
118 /* converts the timer reading to U-Boot ticks */
119 /* the timestamp is the number of ticks since reset */
120 ulong get_timer_masked (void)
122 /* get current count */
123 unsigned long long now = READ_TIMER;
126 /* Must have wrapped */
127 total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
129 total_count += lastdec - now;
135 do_div(now, div_timer);
141 /* waits specified delay value and resets timestamp */
142 void udelay_masked (unsigned long usec)
148 * This function is derived from PowerPC code (read timebase as long long).
149 * On ARM it just returns the timer value.
151 unsigned long long get_ticks(void)
157 * Return the timebase clock frequency
158 * i.e. how often the timer decrements
160 ulong get_tbclk (void)
162 unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
164 do_div(tmp, div_clock);