3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
15 * Philippe Robin, <philippe.robin@arm.com>
17 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/arch/systimer.h>
25 #include <asm/arch/sysctrl.h>
26 #include <asm/arch/wdt.h>
27 #include "../drivers/mmc/arm_pl180_mmci.h"
29 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
30 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
32 static void flash__init(void);
33 static void vexpress_timer_init(void);
34 DECLARE_GLOBAL_DATA_PTR;
36 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
37 void show_boot_progress(int progress)
39 printf("Boot reached stage %d\n", progress);
43 static inline void delay(ulong loops)
45 __asm__ volatile ("1:\n"
47 "bne 1b" : "=r" (loops) : "0" (loops));
52 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
53 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
58 vexpress_timer_init();
63 int board_eth_init(bd_t *bis)
67 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
72 int cpu_mmc_init(bd_t *bis)
76 #ifdef CONFIG_ARM_PL180_MMCI
77 struct pl180_mmc_host *host;
79 host = malloc(sizeof(struct pl180_mmc_host));
82 memset(host, 0, sizeof(*host));
84 strcpy(host->name, "MMC");
85 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
86 host->pwr_init = INIT_PWR;
87 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
88 host->voltages = VOLTAGE_WINDOW_MMC;
90 host->clock_in = ARM_MCLK;
91 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
92 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
93 rc = arm_pl180_mmci_init(host);
98 static void flash__init(void)
100 /* Setup the sytem control register to allow writing to flash */
101 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
102 &sysctrl_base->scflashctrl);
108 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
112 void dram_init_banksize(void)
114 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
115 gd->bd->bi_dram[0].size =
116 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
117 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
118 gd->bd->bi_dram[1].size =
119 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
124 * Setup a 32 bit timer, running at 1KHz
125 * Versatile Express Motherboard provides 1 MHz timer
127 static void vexpress_timer_init(void)
130 * Set clock frequency in system controller:
131 * VEXPRESS_REFCLK is 32KHz
132 * VEXPRESS_TIMCLK is 1MHz
134 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
135 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
136 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
140 * Enabled, free running, no interrupt, 32-bit, wrapping
142 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
143 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
144 writel(SYSTIMER_EN | SYSTIMER_32BIT |
145 readl(&systimer_base->timer0control),
146 &systimer_base->timer0control);
149 int v2m_cfg_write(u32 devfn, u32 data)
151 /* Configuration interface broken? */
154 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
156 val = readl(V2M_SYS_CFGSTAT);
157 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
159 writel(data, V2M_SYS_CFGDATA);
160 writel(devfn, V2M_SYS_CFGCTRL);
163 val = readl(V2M_SYS_CFGSTAT);
166 return !!(val & SYS_CFG_ERR);
169 /* Use the ARM Watchdog System to cause reset */
170 void reset_cpu(ulong addr)
172 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
173 printf("Unable to reboot\n");
176 void lowlevel_init(void)
180 ulong get_board_rev(void){
181 return readl((u32 *)SYS_ID);
184 #ifdef CONFIG_ARMV7_NONSEC
185 /* Setting the address at which secondary cores start from.
186 * Versatile Express uses one address for all cores, so ignore corenr
188 void smp_set_core_boot_addr(unsigned long addr, int corenr)
190 /* The SYSFLAGS register on VExpress needs to be cleared first
191 * by writing to the next address, since any writes to the address
192 * at offset 0 will only be ORed in
194 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
195 writel(addr, CONFIG_SYSFLAGS_ADDR);