3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * 2004 (c) MontaVista Software, Inc.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 DECLARE_GLOBAL_DATA_PTR;
33 /* ------------------------------------------------------------------------- */
36 * Board dependent initialisation
40 #define ECOR_RESET 0x80
41 #define ECOR_LEVEL_IRQ 0x40
42 #define ECOR_WR_ATTRIB 0x04
43 #define ECOR_ENABLE 0x01
46 #define ECSR_IOIS8 0x20
47 #define ECSR_PWRDWN 0x04
49 #define SMC_IO_SHIFT 2
50 #define NCR_0 (*((volatile u_char *)(0x100000a0)))
51 #define NCR_ENET_OSC_EN (1<<3)
54 readb(volatile u8 * p)
60 writeb(u8 v, volatile u8 * p)
70 volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
72 NCR_0 |= NCR_ENET_OSC_EN;
75 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
76 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
80 * The device will ignore all writes to the enable bit while
81 * reset is asserted, even if the reset bit is cleared in the
82 * same write. Must clear reset first, then enable the device.
84 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
85 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
88 * Set the appropriate byte/word mode.
90 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
92 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
105 gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
106 gd->bd->bi_boot_params = 0xc0000100;
116 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
117 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
122 #ifdef CONFIG_CMD_NET
123 int board_eth_init(bd_t *bis)
126 #ifdef CONFIG_LAN91C96
127 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);