3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * 2004 (c) MontaVista Software, Inc.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* ------------------------------------------------------------------------- */
33 * Board dependent initialisation
37 #define ECOR_RESET 0x80
38 #define ECOR_LEVEL_IRQ 0x40
39 #define ECOR_WR_ATTRIB 0x04
40 #define ECOR_ENABLE 0x01
43 #define ECSR_IOIS8 0x20
44 #define ECSR_PWRDWN 0x04
46 #define SMC_IO_SHIFT 2
47 #define NCR_0 (*((volatile u_char *)(0x100000a0)))
48 #define NCR_ENET_OSC_EN (1<<3)
51 readb(volatile u8 * p)
57 writeb(u8 v, volatile u8 * p)
67 volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
69 NCR_0 |= NCR_ENET_OSC_EN;
72 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
73 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
77 * The device will ignore all writes to the enable bit while
78 * reset is asserted, even if the reset bit is cleared in the
79 * same write. Must clear reset first, then enable the device.
81 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
82 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
85 * Set the appropriate byte/word mode.
87 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
89 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
102 DECLARE_GLOBAL_DATA_PTR;
104 gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
105 gd->bd->bi_boot_params = 0xc0000100;
115 DECLARE_GLOBAL_DATA_PTR;
117 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
118 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;