3 * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
4 * w.wegner@astro-kom.de
6 * based on the files by
7 * Heiko Schocher, DENX Software Engineering, hs@denx.de
9 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
10 * Keith Outwater, keith_outwater@mvis.com.
12 * SPDX-License-Identifier: GPL-2.0+
15 /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
23 #include <asm/immap_5329.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 int altera_pre_fn(int cookie)
31 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
32 unsigned char tmp_char;
33 unsigned short tmp_short;
35 /* first, set the required pins to GPIO function */
36 /* PAR_T0IN -> GPIO */
37 tmp_char = readb(&gpiop->par_timer);
39 writeb(tmp_char, &gpiop->par_timer);
40 /* all QSPI pins -> GPIO */
41 writew(0x0000, &gpiop->par_qspi);
42 /* U0RTS, U0CTS -> GPIO */
43 tmp_short = __raw_readw(&gpiop->par_uart);
45 __raw_writew(tmp_short, &gpiop->par_uart);
46 /* all PWM pins -> GPIO */
47 writeb(0x00, &gpiop->par_pwm);
48 /* next, set data direction registers */
49 writeb(0x01, &gpiop->pddr_timer);
50 writeb(0x25, &gpiop->pddr_qspi);
51 writeb(0x0c, &gpiop->pddr_uart);
52 writeb(0x04, &gpiop->pddr_pwm);
54 /* ensure other SPI peripherals are deselected */
55 writeb(0x08, &gpiop->ppd_uart);
56 writeb(0x38, &gpiop->ppd_qspi);
58 /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
59 writeb(0xFB, &gpiop->pclrr_uart);
60 /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
61 writeb(0xFE, &gpiop->pclrr_timer);
62 writeb(0xDF, &gpiop->pclrr_qspi);
66 /* Set the state of CONFIG Pin */
67 int altera_config_fn(int assert_config, int flush, int cookie)
69 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
72 writeb(0x04, &gpiop->ppd_uart);
74 writeb(0xFB, &gpiop->pclrr_uart);
78 /* Returns the state of STATUS Pin */
79 int altera_status_fn(int cookie)
81 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
83 if (readb(&gpiop->ppd_pwm) & 0x08)
88 /* Returns the state of CONF_DONE Pin */
89 int altera_done_fn(int cookie)
91 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
93 if (readb(&gpiop->ppd_pwm) & 0x20)
99 * writes the complete buffer to the FPGA
100 * writing the complete buffer in one function is much faster,
101 * then calling it for every bit
103 int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
105 size_t bytecount = 0;
106 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
107 unsigned char *data = (unsigned char *)buf;
108 unsigned char val = 0;
110 int len_40 = len / 40;
112 while (bytecount < len) {
113 val = data[bytecount++];
116 writeb(0xFB, &gpiop->pclrr_qspi);
118 writeb(0x01, &gpiop->ppd_qspi);
120 writeb(0xFE, &gpiop->pclrr_qspi);
121 writeb(0x04, &gpiop->ppd_qspi);
126 if (bytecount % len_40 == 0) {
127 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
130 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
131 putc('.'); /* let them know we are alive */
133 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
142 /* called, when programming is aborted */
143 int altera_abort_fn(int cookie)
145 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
147 writeb(0x20, &gpiop->ppd_qspi);
148 writeb(0x08, &gpiop->ppd_uart);
152 /* called, when programming was succesful */
153 int altera_post_fn(int cookie)
155 return altera_abort_fn(cookie);
159 * Note that these are pointers to code that is in Flash. They will be
160 * relocated at runtime.
161 * FIXME: relocation not yet working for coldfire, see below!
163 Altera_CYC2_Passive_Serial_fns altera_fns = {
173 Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
182 /* Initialize the fpga. Return 1 on success, 0 on failure. */
183 int astro5373l_altera_load(void)
187 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
189 * I did not yet manage to get relocation work properly,
190 * so set stuff here instead of static initialisation:
192 altera_fns.pre = altera_pre_fn;
193 altera_fns.config = altera_config_fn;
194 altera_fns.status = altera_status_fn;
195 altera_fns.done = altera_done_fn;
196 altera_fns.write = altera_write_fn;
197 altera_fns.abort = altera_abort_fn;
198 altera_fns.post = altera_post_fn;
199 altera_fpga[i].iface_fns = (void *)&altera_fns;
200 fpga_add(fpga_altera, &altera_fpga[i]);
205 /* Set the FPGA's PROG_B line to the specified level */
206 int xilinx_pgm_config_fn(int assert, int flush, int cookie)
208 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
211 writeb(0xFB, &gpiop->pclrr_uart);
213 writeb(0x04, &gpiop->ppd_uart);
218 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
221 int xilinx_init_config_fn(int cookie)
223 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
225 return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
228 /* Test the state of the active-high FPGA DONE pin */
229 int xilinx_done_config_fn(int cookie)
231 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
233 return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
236 /* Abort an FPGA operation */
237 int xilinx_abort_config_fn(int cookie)
239 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
240 /* ensure all SPI peripherals and FPGAs are deselected */
241 writeb(0x08, &gpiop->ppd_uart);
242 writeb(0x01, &gpiop->ppd_timer);
243 writeb(0x38, &gpiop->ppd_qspi);
248 * FPGA pre-configuration function. Just make sure that
249 * FPGA reset is asserted to keep the FPGA from starting up after
252 int xilinx_pre_config_fn(int cookie)
254 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
255 unsigned char tmp_char;
256 unsigned short tmp_short;
258 /* first, set the required pins to GPIO function */
259 /* PAR_T0IN -> GPIO */
260 tmp_char = readb(&gpiop->par_timer);
262 writeb(tmp_char, &gpiop->par_timer);
263 /* all QSPI pins -> GPIO */
264 writew(0x0000, &gpiop->par_qspi);
265 /* U0RTS, U0CTS -> GPIO */
266 tmp_short = __raw_readw(&gpiop->par_uart);
268 __raw_writew(tmp_short, &gpiop->par_uart);
269 /* all PWM pins -> GPIO */
270 writeb(0x00, &gpiop->par_pwm);
271 /* next, set data direction registers */
272 writeb(0x01, &gpiop->pddr_timer);
273 writeb(0x25, &gpiop->pddr_qspi);
274 writeb(0x0c, &gpiop->pddr_uart);
275 writeb(0x04, &gpiop->pddr_pwm);
277 /* ensure other SPI peripherals are deselected */
278 writeb(0x08, &gpiop->ppd_uart);
279 writeb(0x38, &gpiop->ppd_qspi);
280 writeb(0x01, &gpiop->ppd_timer);
282 /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
283 writeb(0xFB, &gpiop->pclrr_uart);
284 /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
285 writeb(0xF7, &gpiop->pclrr_uart);
286 writeb(0xDF, &gpiop->pclrr_qspi);
291 * FPGA post configuration function. Should perform a test if FPGA is running.
293 int xilinx_post_config_fn(int cookie)
303 int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
305 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
308 writeb(0x04, &gpiop->ppd_qspi);
310 writeb(0xFB, &gpiop->pclrr_qspi);
314 int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
316 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
319 writeb(0x01, &gpiop->ppd_qspi);
321 writeb(0xFE, &gpiop->pclrr_qspi);
325 int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
327 size_t bytecount = 0;
328 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
329 unsigned char *data = (unsigned char *)buf;
330 unsigned char val = 0;
332 int len_40 = len / 40;
334 for (bytecount = 0; bytecount < len; bytecount++) {
336 for (i = 8; i > 0; i--) {
337 writeb(0xFB, &gpiop->pclrr_qspi);
339 writeb(0x01, &gpiop->ppd_qspi);
341 writeb(0xFE, &gpiop->pclrr_qspi);
342 writeb(0x04, &gpiop->ppd_qspi);
345 if (bytecount % len_40 == 0) {
346 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
349 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
350 putc('.'); /* let them know we are alive */
352 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
362 * Note that these are pointers to code that is in Flash. They will be
363 * relocated at runtime.
364 * FIXME: relocation not yet working for coldfire, see below!
366 xilinx_spartan3_slave_serial_fns xilinx_fns = {
367 xilinx_pre_config_fn,
368 xilinx_pgm_config_fn,
369 xilinx_clk_config_fn,
370 xilinx_init_config_fn,
371 xilinx_done_config_fn,
374 xilinx_fastwr_config_fn
377 xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
380 XILINX_XC3S4000_SIZE,
386 /* Initialize the fpga. Return 1 on success, 0 on failure. */
387 int astro5373l_xilinx_load(void)
393 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
395 * I did not yet manage to get relocation work properly,
396 * so set stuff here instead of static initialisation:
398 xilinx_fns.pre = xilinx_pre_config_fn;
399 xilinx_fns.pgm = xilinx_pgm_config_fn;
400 xilinx_fns.clk = xilinx_clk_config_fn;
401 xilinx_fns.init = xilinx_init_config_fn;
402 xilinx_fns.done = xilinx_done_config_fn;
403 xilinx_fns.wr = xilinx_wr_config_fn;
404 xilinx_fns.bwr = xilinx_fastwr_config_fn;
405 xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
406 fpga_add(fpga_xilinx, &xilinx_fpga[i]);