3 * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
4 * w.wegner@astro-kom.de
6 * based on the files by
7 * Heiko Schocher, DENX Software Engineering, hs@denx.de
9 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
10 * Keith Outwater, keith_outwater@mvis.com.
12 * SPDX-License-Identifier: GPL-2.0+
15 /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
24 #include <asm/immap_5329.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 int altera_pre_fn(int cookie)
32 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
33 unsigned char tmp_char;
34 unsigned short tmp_short;
36 /* first, set the required pins to GPIO function */
37 /* PAR_T0IN -> GPIO */
38 tmp_char = readb(&gpiop->par_timer);
40 writeb(tmp_char, &gpiop->par_timer);
41 /* all QSPI pins -> GPIO */
42 writew(0x0000, &gpiop->par_qspi);
43 /* U0RTS, U0CTS -> GPIO */
44 tmp_short = __raw_readw(&gpiop->par_uart);
46 __raw_writew(tmp_short, &gpiop->par_uart);
47 /* all PWM pins -> GPIO */
48 writeb(0x00, &gpiop->par_pwm);
49 /* next, set data direction registers */
50 writeb(0x01, &gpiop->pddr_timer);
51 writeb(0x25, &gpiop->pddr_qspi);
52 writeb(0x0c, &gpiop->pddr_uart);
53 writeb(0x04, &gpiop->pddr_pwm);
55 /* ensure other SPI peripherals are deselected */
56 writeb(0x08, &gpiop->ppd_uart);
57 writeb(0x38, &gpiop->ppd_qspi);
59 /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
60 writeb(0xFB, &gpiop->pclrr_uart);
61 /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
62 writeb(0xFE, &gpiop->pclrr_timer);
63 writeb(0xDF, &gpiop->pclrr_qspi);
67 /* Set the state of CONFIG Pin */
68 int altera_config_fn(int assert_config, int flush, int cookie)
70 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
73 writeb(0x04, &gpiop->ppd_uart);
75 writeb(0xFB, &gpiop->pclrr_uart);
79 /* Returns the state of STATUS Pin */
80 int altera_status_fn(int cookie)
82 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
84 if (readb(&gpiop->ppd_pwm) & 0x08)
89 /* Returns the state of CONF_DONE Pin */
90 int altera_done_fn(int cookie)
92 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
94 if (readb(&gpiop->ppd_pwm) & 0x20)
100 * writes the complete buffer to the FPGA
101 * writing the complete buffer in one function is much faster,
102 * then calling it for every bit
104 int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
106 size_t bytecount = 0;
107 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
108 unsigned char *data = (unsigned char *)buf;
109 unsigned char val = 0;
111 int len_40 = len / 40;
113 while (bytecount < len) {
114 val = data[bytecount++];
117 writeb(0xFB, &gpiop->pclrr_qspi);
119 writeb(0x01, &gpiop->ppd_qspi);
121 writeb(0xFE, &gpiop->pclrr_qspi);
122 writeb(0x04, &gpiop->ppd_qspi);
127 if (bytecount % len_40 == 0) {
128 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
131 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
132 putc('.'); /* let them know we are alive */
134 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
143 /* called, when programming is aborted */
144 int altera_abort_fn(int cookie)
146 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
148 writeb(0x20, &gpiop->ppd_qspi);
149 writeb(0x08, &gpiop->ppd_uart);
153 /* called, when programming was succesful */
154 int altera_post_fn(int cookie)
156 return altera_abort_fn(cookie);
160 * Note that these are pointers to code that is in Flash. They will be
161 * relocated at runtime.
162 * FIXME: relocation not yet working for coldfire, see below!
164 Altera_CYC2_Passive_Serial_fns altera_fns = {
174 Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
183 /* Initialize the fpga. Return 1 on success, 0 on failure. */
184 int astro5373l_altera_load(void)
188 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
190 * I did not yet manage to get relocation work properly,
191 * so set stuff here instead of static initialisation:
193 altera_fns.pre = altera_pre_fn;
194 altera_fns.config = altera_config_fn;
195 altera_fns.status = altera_status_fn;
196 altera_fns.done = altera_done_fn;
197 altera_fns.write = altera_write_fn;
198 altera_fns.abort = altera_abort_fn;
199 altera_fns.post = altera_post_fn;
200 altera_fpga[i].iface_fns = (void *)&altera_fns;
201 fpga_add(fpga_altera, &altera_fpga[i]);
206 /* Set the FPGA's PROG_B line to the specified level */
207 int xilinx_pgm_config_fn(int assert, int flush, int cookie)
209 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
212 writeb(0xFB, &gpiop->pclrr_uart);
214 writeb(0x04, &gpiop->ppd_uart);
219 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
222 int xilinx_init_config_fn(int cookie)
224 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
226 return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
229 /* Test the state of the active-high FPGA DONE pin */
230 int xilinx_done_config_fn(int cookie)
232 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
234 return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
237 /* Abort an FPGA operation */
238 int xilinx_abort_config_fn(int cookie)
240 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
241 /* ensure all SPI peripherals and FPGAs are deselected */
242 writeb(0x08, &gpiop->ppd_uart);
243 writeb(0x01, &gpiop->ppd_timer);
244 writeb(0x38, &gpiop->ppd_qspi);
249 * FPGA pre-configuration function. Just make sure that
250 * FPGA reset is asserted to keep the FPGA from starting up after
253 int xilinx_pre_config_fn(int cookie)
255 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
256 unsigned char tmp_char;
257 unsigned short tmp_short;
259 /* first, set the required pins to GPIO function */
260 /* PAR_T0IN -> GPIO */
261 tmp_char = readb(&gpiop->par_timer);
263 writeb(tmp_char, &gpiop->par_timer);
264 /* all QSPI pins -> GPIO */
265 writew(0x0000, &gpiop->par_qspi);
266 /* U0RTS, U0CTS -> GPIO */
267 tmp_short = __raw_readw(&gpiop->par_uart);
269 __raw_writew(tmp_short, &gpiop->par_uart);
270 /* all PWM pins -> GPIO */
271 writeb(0x00, &gpiop->par_pwm);
272 /* next, set data direction registers */
273 writeb(0x01, &gpiop->pddr_timer);
274 writeb(0x25, &gpiop->pddr_qspi);
275 writeb(0x0c, &gpiop->pddr_uart);
276 writeb(0x04, &gpiop->pddr_pwm);
278 /* ensure other SPI peripherals are deselected */
279 writeb(0x08, &gpiop->ppd_uart);
280 writeb(0x38, &gpiop->ppd_qspi);
281 writeb(0x01, &gpiop->ppd_timer);
283 /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
284 writeb(0xFB, &gpiop->pclrr_uart);
285 /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
286 writeb(0xF7, &gpiop->pclrr_uart);
287 writeb(0xDF, &gpiop->pclrr_qspi);
292 * FPGA post configuration function. Should perform a test if FPGA is running.
294 int xilinx_post_config_fn(int cookie)
304 int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
306 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
309 writeb(0x04, &gpiop->ppd_qspi);
311 writeb(0xFB, &gpiop->pclrr_qspi);
315 int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
317 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
320 writeb(0x01, &gpiop->ppd_qspi);
322 writeb(0xFE, &gpiop->pclrr_qspi);
326 int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
328 size_t bytecount = 0;
329 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
330 unsigned char *data = (unsigned char *)buf;
331 unsigned char val = 0;
333 int len_40 = len / 40;
335 for (bytecount = 0; bytecount < len; bytecount++) {
337 for (i = 8; i > 0; i--) {
338 writeb(0xFB, &gpiop->pclrr_qspi);
340 writeb(0x01, &gpiop->ppd_qspi);
342 writeb(0xFE, &gpiop->pclrr_qspi);
343 writeb(0x04, &gpiop->ppd_qspi);
346 if (bytecount % len_40 == 0) {
347 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
350 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
351 putc('.'); /* let them know we are alive */
353 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
363 * Note that these are pointers to code that is in Flash. They will be
364 * relocated at runtime.
365 * FIXME: relocation not yet working for coldfire, see below!
367 xilinx_spartan3_slave_serial_fns xilinx_fns = {
368 xilinx_pre_config_fn,
369 xilinx_pgm_config_fn,
370 xilinx_clk_config_fn,
371 xilinx_init_config_fn,
372 xilinx_done_config_fn,
375 xilinx_fastwr_config_fn
378 xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
381 XILINX_XC3S4000_SIZE,
387 /* Initialize the fpga. Return 1 on success, 0 on failure. */
388 int astro5373l_xilinx_load(void)
394 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
396 * I did not yet manage to get relocation work properly,
397 * so set stuff here instead of static initialisation:
399 xilinx_fns.pre = xilinx_pre_config_fn;
400 xilinx_fns.pgm = xilinx_pgm_config_fn;
401 xilinx_fns.clk = xilinx_clk_config_fn;
402 xilinx_fns.init = xilinx_init_config_fn;
403 xilinx_fns.done = xilinx_done_config_fn;
404 xilinx_fns.wr = xilinx_wr_config_fn;
405 xilinx_fns.bwr = xilinx_fastwr_config_fn;
406 xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
407 fpga_add(fpga_xilinx, &xilinx_fpga[i]);