1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
5 * w.wegner@astro-kom.de
7 * based on the files by
8 * Heiko Schocher, DENX Software Engineering, hs@denx.de
10 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
11 * Keith Outwater, keith_outwater@mvis.com.
14 /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
23 #include <asm/immap_5329.h>
27 int altera_pre_fn(int cookie)
29 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
30 unsigned char tmp_char;
31 unsigned short tmp_short;
33 /* first, set the required pins to GPIO function */
34 /* PAR_T0IN -> GPIO */
35 tmp_char = readb(&gpiop->par_timer);
37 writeb(tmp_char, &gpiop->par_timer);
38 /* all QSPI pins -> GPIO */
39 writew(0x0000, &gpiop->par_qspi);
40 /* U0RTS, U0CTS -> GPIO */
41 tmp_short = __raw_readw(&gpiop->par_uart);
43 __raw_writew(tmp_short, &gpiop->par_uart);
44 /* all PWM pins -> GPIO */
45 writeb(0x00, &gpiop->par_pwm);
46 /* next, set data direction registers */
47 writeb(0x01, &gpiop->pddr_timer);
48 writeb(0x25, &gpiop->pddr_qspi);
49 writeb(0x0c, &gpiop->pddr_uart);
50 writeb(0x04, &gpiop->pddr_pwm);
52 /* ensure other SPI peripherals are deselected */
53 writeb(0x08, &gpiop->ppd_uart);
54 writeb(0x38, &gpiop->ppd_qspi);
56 /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
57 writeb(0xFB, &gpiop->pclrr_uart);
58 /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
59 writeb(0xFE, &gpiop->pclrr_timer);
60 writeb(0xDF, &gpiop->pclrr_qspi);
64 /* Set the state of CONFIG Pin */
65 int altera_config_fn(int assert_config, int flush, int cookie)
67 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
70 writeb(0x04, &gpiop->ppd_uart);
72 writeb(0xFB, &gpiop->pclrr_uart);
76 /* Returns the state of STATUS Pin */
77 int altera_status_fn(int cookie)
79 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
81 if (readb(&gpiop->ppd_pwm) & 0x08)
86 /* Returns the state of CONF_DONE Pin */
87 int altera_done_fn(int cookie)
89 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
91 if (readb(&gpiop->ppd_pwm) & 0x20)
97 * writes the complete buffer to the FPGA
98 * writing the complete buffer in one function is much faster,
99 * then calling it for every bit
101 int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
103 size_t bytecount = 0;
104 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
105 unsigned char *data = (unsigned char *)buf;
106 unsigned char val = 0;
108 int len_40 = len / 40;
110 while (bytecount < len) {
111 val = data[bytecount++];
114 writeb(0xFB, &gpiop->pclrr_qspi);
116 writeb(0x01, &gpiop->ppd_qspi);
118 writeb(0xFE, &gpiop->pclrr_qspi);
119 writeb(0x04, &gpiop->ppd_qspi);
124 if (bytecount % len_40 == 0) {
125 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
128 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
129 putc('.'); /* let them know we are alive */
131 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
140 /* called, when programming is aborted */
141 int altera_abort_fn(int cookie)
143 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
145 writeb(0x20, &gpiop->ppd_qspi);
146 writeb(0x08, &gpiop->ppd_uart);
150 /* called, when programming was succesful */
151 int altera_post_fn(int cookie)
153 return altera_abort_fn(cookie);
157 * Note that these are pointers to code that is in Flash. They will be
158 * relocated at runtime.
159 * FIXME: relocation not yet working for coldfire, see below!
161 Altera_CYC2_Passive_Serial_fns altera_fns = {
171 Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
180 /* Initialize the fpga. Return 1 on success, 0 on failure. */
181 int astro5373l_altera_load(void)
185 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
187 * I did not yet manage to get relocation work properly,
188 * so set stuff here instead of static initialisation:
190 altera_fns.pre = altera_pre_fn;
191 altera_fns.config = altera_config_fn;
192 altera_fns.status = altera_status_fn;
193 altera_fns.done = altera_done_fn;
194 altera_fns.write = altera_write_fn;
195 altera_fns.abort = altera_abort_fn;
196 altera_fns.post = altera_post_fn;
197 altera_fpga[i].iface_fns = (void *)&altera_fns;
198 fpga_add(fpga_altera, &altera_fpga[i]);
203 /* Set the FPGA's PROG_B line to the specified level */
204 int xilinx_pgm_config_fn(int assert, int flush, int cookie)
206 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
209 writeb(0xFB, &gpiop->pclrr_uart);
211 writeb(0x04, &gpiop->ppd_uart);
216 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
219 int xilinx_init_config_fn(int cookie)
221 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
223 return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
226 /* Test the state of the active-high FPGA DONE pin */
227 int xilinx_done_config_fn(int cookie)
229 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
231 return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
234 /* Abort an FPGA operation */
235 int xilinx_abort_config_fn(int cookie)
237 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
238 /* ensure all SPI peripherals and FPGAs are deselected */
239 writeb(0x08, &gpiop->ppd_uart);
240 writeb(0x01, &gpiop->ppd_timer);
241 writeb(0x38, &gpiop->ppd_qspi);
246 * FPGA pre-configuration function. Just make sure that
247 * FPGA reset is asserted to keep the FPGA from starting up after
250 int xilinx_pre_config_fn(int cookie)
252 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
253 unsigned char tmp_char;
254 unsigned short tmp_short;
256 /* first, set the required pins to GPIO function */
257 /* PAR_T0IN -> GPIO */
258 tmp_char = readb(&gpiop->par_timer);
260 writeb(tmp_char, &gpiop->par_timer);
261 /* all QSPI pins -> GPIO */
262 writew(0x0000, &gpiop->par_qspi);
263 /* U0RTS, U0CTS -> GPIO */
264 tmp_short = __raw_readw(&gpiop->par_uart);
266 __raw_writew(tmp_short, &gpiop->par_uart);
267 /* all PWM pins -> GPIO */
268 writeb(0x00, &gpiop->par_pwm);
269 /* next, set data direction registers */
270 writeb(0x01, &gpiop->pddr_timer);
271 writeb(0x25, &gpiop->pddr_qspi);
272 writeb(0x0c, &gpiop->pddr_uart);
273 writeb(0x04, &gpiop->pddr_pwm);
275 /* ensure other SPI peripherals are deselected */
276 writeb(0x08, &gpiop->ppd_uart);
277 writeb(0x38, &gpiop->ppd_qspi);
278 writeb(0x01, &gpiop->ppd_timer);
280 /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
281 writeb(0xFB, &gpiop->pclrr_uart);
282 /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
283 writeb(0xF7, &gpiop->pclrr_uart);
284 writeb(0xDF, &gpiop->pclrr_qspi);
289 * FPGA post configuration function. Should perform a test if FPGA is running.
291 int xilinx_post_config_fn(int cookie)
301 int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
303 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
306 writeb(0x04, &gpiop->ppd_qspi);
308 writeb(0xFB, &gpiop->pclrr_qspi);
312 int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
314 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
317 writeb(0x01, &gpiop->ppd_qspi);
319 writeb(0xFE, &gpiop->pclrr_qspi);
323 int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
325 size_t bytecount = 0;
326 gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
327 unsigned char *data = (unsigned char *)buf;
328 unsigned char val = 0;
330 int len_40 = len / 40;
332 for (bytecount = 0; bytecount < len; bytecount++) {
334 for (i = 8; i > 0; i--) {
335 writeb(0xFB, &gpiop->pclrr_qspi);
337 writeb(0x01, &gpiop->ppd_qspi);
339 writeb(0xFE, &gpiop->pclrr_qspi);
340 writeb(0x04, &gpiop->ppd_qspi);
343 if (bytecount % len_40 == 0) {
344 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
347 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
348 putc('.'); /* let them know we are alive */
350 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
360 * Note that these are pointers to code that is in Flash. They will be
361 * relocated at runtime.
362 * FIXME: relocation not yet working for coldfire, see below!
364 xilinx_spartan3_slave_serial_fns xilinx_fns = {
365 xilinx_pre_config_fn,
366 xilinx_pgm_config_fn,
367 xilinx_clk_config_fn,
368 xilinx_init_config_fn,
369 xilinx_done_config_fn,
372 xilinx_fastwr_config_fn
375 xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
378 XILINX_XC3S4000_SIZE,
384 /* Initialize the fpga. Return 1 on success, 0 on failure. */
385 int astro5373l_xilinx_load(void)
391 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
393 * I did not yet manage to get relocation work properly,
394 * so set stuff here instead of static initialisation:
396 xilinx_fns.pre = xilinx_pre_config_fn;
397 xilinx_fns.pgm = xilinx_pgm_config_fn;
398 xilinx_fns.clk = xilinx_clk_config_fn;
399 xilinx_fns.init = xilinx_init_config_fn;
400 xilinx_fns.done = xilinx_done_config_fn;
401 xilinx_fns.wr = xilinx_wr_config_fn;
402 xilinx_fns.bwr = xilinx_fastwr_config_fn;
403 xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
404 fpga_add(fpga_xilinx, &xilinx_fpga[i]);