3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
28 #ifdef CONFIG_DRIVER_ETHER
30 #if (CONFIG_COMMANDS & CFG_CMD_NET)
34 * dm9161_IsPhyConnected
36 * Reads the 2 PHY ID registers
38 * p_mac - pointer to AT91S_EMAC struct
40 * TRUE - if id read successfully
43 static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
45 unsigned short Id1, Id2;
47 at91rm9200_EmacEnableMDIO (p_mac);
48 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
49 at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
50 at91rm9200_EmacDisableMDIO (p_mac);
52 if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
53 ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
63 * Link parallel detection status of MAC is checked and set in the
64 * MAC configuration registers
66 * p_mac - pointer to MAC
68 * TRUE - if link status set succesfully
69 * FALSE - if link status not set
71 static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
73 unsigned short stat1, stat2;
75 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
78 if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
81 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
84 if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
85 /*set Emac for 100BaseTX and Full Duplex */
86 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
90 if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
91 /*set MII for 10BaseT and Full Duplex */
92 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
93 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
98 if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
99 /*set MII for 100BaseTX and Half Duplex */
100 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
101 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
106 if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
107 /*set MII for 10BaseT and Half Duplex */
108 p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
119 * MAC starts checking its link by using parallel detection and
120 * Autonegotiation and the same is set in the MAC configuration registers
122 * p_mac - pointer to struct AT91S_EMAC
124 * TRUE - if link status set succesfully
125 * FALSE - if link status not set
127 static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
130 unsigned short IntValue;
132 at91rm9200_EmacEnableMDIO (p_mac);
134 if (!dm9161_GetLinkSpeed (p_mac)) {
135 /* Try another time */
136 ret = dm9161_GetLinkSpeed (p_mac);
139 /* Disable PHY Interrupts */
140 at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
141 /* clear FDX, SPD, Link, INTR masks */
142 IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
143 DM9161_LINK_MASK | DM9161_INTR_MASK);
144 at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
145 at91rm9200_EmacDisableMDIO (p_mac);
153 * dm9161_AutoNegotiate
155 * MAC Autonegotiates with the partner status of same is set in the
156 * MAC configuration registers
158 * dev - pointer to struct net_device
160 * TRUE - if link status set successfully
161 * FALSE - if link status not set
163 static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
165 unsigned short value;
166 unsigned short PhyAnar;
167 unsigned short PhyAnalpar;
169 /* Set dm9161 control register */
170 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
172 value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
173 value |= DM9161_ISOLATE; /* Electrically isolate PHY */
174 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
177 /* Set the Auto_negotiation Advertisement Register */
178 /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
179 PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
180 DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
181 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
184 /* Read the Control Register */
185 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
188 value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
189 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
191 /* Restart Auto_negotiation */
192 value |= DM9161_RESTART_AUTONEG;
193 if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
196 /*check AutoNegotiate complete */
198 at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
199 if (!(value & DM9161_AUTONEG_COMP))
202 /* Get the AutoNeg Link partner base page */
203 if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
206 if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
207 /*set MII for 100BaseTX and Full Duplex */
208 p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
212 if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
213 /*set MII for 10BaseT and Full Duplex */
214 p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
215 ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
225 * at91rm92000_GetPhyInterface
227 * Initialise the interface functions to the PHY
233 void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
235 p_phyops->Init = dm9161_InitPhy;
236 p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
237 p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
238 p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
241 #endif /* CONFIG_COMMANDS & CFG_CMD_NET */
243 #endif /* CONFIG_DRIVER_ETHER */