2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91cap9.h>
27 #include <asm/arch/at91cap9_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/io.h>
34 #include <atmel_lcdc.h>
35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 #define MP_BLOCK_3_BASE 0xFDF00000
41 DECLARE_GLOBAL_DATA_PTR;
43 /* ------------------------------------------------------------------------- */
45 * Miscelaneous platform dependent initialisations
48 static void at91cap9_serial_hw_init(void)
51 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
52 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
53 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
57 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
58 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
59 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
63 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
64 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
65 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
68 #ifdef CONFIG_USART3 /* DBGU */
69 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
70 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
71 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
75 static void at91cap9_nor_hw_init(void)
79 /* Ensure EBI supply is 3.3V */
80 csa = at91_sys_read(AT91_MATRIX_EBICSA);
81 at91_sys_write(AT91_MATRIX_EBICSA,
82 csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
83 /* Configure SMC CS0 for parallel flash */
84 at91_sys_write(AT91_SMC_SETUP(0),
85 AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
86 AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
87 at91_sys_write(AT91_SMC_PULSE(0),
88 AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
89 AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
90 at91_sys_write(AT91_SMC_CYCLE(0),
91 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
92 at91_sys_write(AT91_SMC_MODE(0),
93 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
94 AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
95 AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
98 #ifdef CONFIG_CMD_NAND
99 static void at91cap9_nand_hw_init(void)
104 csa = at91_sys_read(AT91_MATRIX_EBICSA);
105 at91_sys_write(AT91_MATRIX_EBICSA,
106 csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
107 AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
109 /* Configure SMC CS3 for NAND/SmartMedia */
110 at91_sys_write(AT91_SMC_SETUP(3),
111 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
112 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
113 at91_sys_write(AT91_SMC_PULSE(3),
114 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
115 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
116 at91_sys_write(AT91_SMC_CYCLE(3),
117 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
118 at91_sys_write(AT91_SMC_MODE(3),
119 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
120 AT91_SMC_EXNWMODE_DISABLE |
121 #ifdef CFG_NAND_DBW_16
123 #else /* CFG_NAND_DBW_8 */
128 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
130 /* RDY/BSY is not connected */
132 /* Enable NandFlash */
133 at91_set_gpio_output(AT91_PIN_PD15, 1);
137 #ifdef CONFIG_HAS_DATAFLASH
138 static void at91cap9_spi_hw_init(void)
140 at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
142 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
143 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
144 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
147 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
152 static void at91cap9_macb_hw_init(void)
155 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
158 * Disable pull-up on:
159 * RXDV (PB22) => PHY normal mode (not Test mode)
160 * ERX0 (PB25) => PHY ADDR0
161 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
163 * PHY has internal pull-down
165 writel(pin_to_mask(AT91_PIN_PB22) |
166 pin_to_mask(AT91_PIN_PB25) |
167 pin_to_mask(AT91_PIN_PB26),
168 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
170 /* Need to reset PHY -> 500ms reset */
171 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
172 AT91_RSTC_ERSTL | (0x0D << 8) |
175 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
177 /* Wait for end hardware reset */
178 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
180 /* Re-enable pull-up */
181 writel(pin_to_mask(AT91_PIN_PB22) |
182 pin_to_mask(AT91_PIN_PB25) |
183 pin_to_mask(AT91_PIN_PB26),
184 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
186 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
187 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
188 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
189 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
190 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
191 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
192 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
193 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
194 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
195 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
198 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
199 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
200 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
201 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
202 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
203 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
204 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
205 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
207 /* Unlock EMAC, 3 0 2 1 sequence */
208 #define MP_MAC_KEY0 0x5969cb2a
209 #define MP_MAC_KEY1 0xb4a1872e
210 #define MP_MAC_KEY2 0x05683fbc
211 #define MP_MAC_KEY3 0x3634fba4
212 #define UNLOCK_MAC 0x00000008
213 writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
214 writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
215 writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
216 writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
217 writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
221 #ifdef CONFIG_USB_OHCI_NEW
222 static void at91cap9_uhp_hw_init(void)
224 /* Unlock USB OHCI, 3 2 0 1 sequence */
225 #define MP_OHCI_KEY0 0x896c11ca
226 #define MP_OHCI_KEY1 0x68ebca21
227 #define MP_OHCI_KEY2 0x4823efbc
228 #define MP_OHCI_KEY3 0x8651aae4
229 #define UNLOCK_OHCI 0x00000010
230 writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
231 writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
232 writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
233 writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
234 writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
239 vidinfo_t panel_info = {
243 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
244 ATMEL_LCDC_INVFRAME_INVERTED,
253 mmio: AT91CAP9_LCDC_BASE,
256 void lcd_enable(void)
258 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
261 void lcd_disable(void)
263 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
266 static void at91cap9_lcd_hw_init(void)
268 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
269 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
270 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
271 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
272 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
273 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
274 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
275 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
276 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
277 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
278 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
279 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
280 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
281 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
282 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
283 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
284 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
285 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
286 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
287 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
288 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
289 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
291 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
302 /* arch number of AT91CAP9ADK-Board */
303 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
304 /* adress of boot parameters */
305 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
307 at91cap9_serial_hw_init();
308 at91cap9_nor_hw_init();
309 #ifdef CONFIG_CMD_NAND
310 at91cap9_nand_hw_init();
312 #ifdef CONFIG_HAS_DATAFLASH
313 at91cap9_spi_hw_init();
316 at91cap9_macb_hw_init();
318 #ifdef CONFIG_USB_OHCI_NEW
319 at91cap9_uhp_hw_init();
322 at91cap9_lcd_hw_init();
329 gd->bd->bi_dram[0].start = PHYS_SDRAM;
330 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
334 #ifdef CONFIG_RESET_PHY_R
339 * Initialize ethernet HW addr prior to starting Linux,