git.sur5r.net Git - u-boot/blob - board/atmel/at91cap9adk/at91cap9adk.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91cap9.h>
  27 #include <asm/arch/at91cap9_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_common.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <asm/arch/hardware.h>
  35 #include <lcd.h>
  36 #include <atmel_lcdc.h>
  37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  38 #include <net.h>
  39 #endif
  40 #include <netdev.h>
  41
  42 #define MP_BLOCK_3_BASE 0xFDF00000
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* ------------------------------------------------------------------------- */
  47 /*
  48  * Miscelaneous platform dependent initialisations
  49  */
  50
  51 static void at91cap9_slowclock_hw_init(void)
  52 {
  53         /*
  54          * On AT91CAP9 revC CPUs, the slow clock can be based on an
  55          * internal impreciseRC oscillator or an external 32kHz oscillator.
  56          * Switch to the latter.
  57          */
  58 #define ARCH_ID_AT91CAP9_REVB   0x399
  59 #define ARCH_ID_AT91CAP9_REVC   0x601
  60         if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
  61                 unsigned i, tmp = at91_sys_read(AT91_SCKCR);
  62                 if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
  63                         extern void timer_init(void);
  64                         timer_init();
  65                         tmp |= AT91CAP9_SCKCR_OSC32EN;
  66                         at91_sys_write(AT91_SCKCR, tmp);
  67                         for (i = 0; i < 1200; i++)
  68                                 udelay(1000);
  69                         tmp |= AT91CAP9_SCKCR_OSCSEL_32;
  70                         at91_sys_write(AT91_SCKCR, tmp);
  71                         udelay(200);
  72                         tmp &= ~AT91CAP9_SCKCR_RCEN;
  73                         at91_sys_write(AT91_SCKCR, tmp);
  74                 }
  75         }
  76 }
  77
  78 static void at91cap9_nor_hw_init(void)
  79 {
  80         unsigned long csa;
  81
  82         /* Ensure EBI supply is 3.3V */
  83         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  84         at91_sys_write(AT91_MATRIX_EBICSA,
  85                        csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
  86         /* Configure SMC CS0 for parallel flash */
  87         at91_sys_write(AT91_SMC_SETUP(0),
  88                        AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
  89                        AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
  90         at91_sys_write(AT91_SMC_PULSE(0),
  91                        AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
  92                        AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
  93         at91_sys_write(AT91_SMC_CYCLE(0),
  94                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
  95         at91_sys_write(AT91_SMC_MODE(0),
  96                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  97                        AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
  98                        AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
  99 }
 100
 101 #ifdef CONFIG_CMD_NAND
 102 static void at91cap9_nand_hw_init(void)
 103 {
 104         unsigned long csa;
 105
 106         /* Enable CS3 */
 107         csa = at91_sys_read(AT91_MATRIX_EBICSA);
 108         at91_sys_write(AT91_MATRIX_EBICSA,
 109                        csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
 110                        AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 111
 112         /* Configure SMC CS3 for NAND/SmartMedia */
 113         at91_sys_write(AT91_SMC_SETUP(3),
 114                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
 115                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
 116         at91_sys_write(AT91_SMC_PULSE(3),
 117                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
 118                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
 119         at91_sys_write(AT91_SMC_CYCLE(3),
 120                        AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
 121         at91_sys_write(AT91_SMC_MODE(3),
 122                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 123                        AT91_SMC_EXNWMODE_DISABLE |
 124 #ifdef CONFIG_SYS_NAND_DBW_16
 125                        AT91_SMC_DBW_16 |
 126 #else /* CONFIG_SYS_NAND_DBW_8 */
 127                        AT91_SMC_DBW_8 |
 128 #endif
 129                        AT91_SMC_TDF_(1));
 130
 131         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
 132
 133         /* RDY/BSY is not connected */
 134
 135         /* Enable NandFlash */
 136         at91_set_gpio_output(AT91_PIN_PD15, 1);
 137 }
 138 #endif
 139
 140 #ifdef CONFIG_HAS_DATAFLASH
 141 static void at91cap9_spi_hw_init(void)
 142 {
 143         at91_set_B_periph(AT91_PIN_PA5, 0);     /* SPI0_NPCS0 */
 144
 145         at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 146         at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 147         at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 148
 149         /* Enable clock */
 150         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
 151 }
 152 #endif
 153
 154 #ifdef CONFIG_MACB
 155 static void at91cap9_macb_hw_init(void)
 156 {
 157         /* Enable clock */
 158         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
 159
 160         /*
 161          * Disable pull-up on:
 162          *      RXDV (PB22) => PHY normal mode (not Test mode)
 163          *      ERX0 (PB25) => PHY ADDR0
 164          *      ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 165          *
 166          * PHY has internal pull-down
 167          */
 168         writel(pin_to_mask(AT91_PIN_PB22) |
 169                pin_to_mask(AT91_PIN_PB25) |
 170                pin_to_mask(AT91_PIN_PB26),
 171                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 172
 173         /* Need to reset PHY -> 500ms reset */
 174         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 175                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 176                                      AT91_RSTC_URSTEN);
 177
 178         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 179
 180         /* Wait for end hardware reset */
 181         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 182
 183         /* Restore NRST value */
 184         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 185                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
 186                                      AT91_RSTC_URSTEN);
 187
 188         /* Re-enable pull-up */
 189         writel(pin_to_mask(AT91_PIN_PB22) |
 190                pin_to_mask(AT91_PIN_PB25) |
 191                pin_to_mask(AT91_PIN_PB26),
 192                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 193
 194         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
 195         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
 196         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
 197         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
 198         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
 199         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
 200         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
 201         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
 202         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
 203         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
 204
 205 #ifndef CONFIG_RMII
 206         at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
 207         at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 208         at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 209         at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 210         at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 211         at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 212         at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 213         at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 214 #endif
 215         /* Unlock EMAC, 3 0 2 1 sequence */
 216 #define MP_MAC_KEY0     0x5969cb2a
 217 #define MP_MAC_KEY1     0xb4a1872e
 218 #define MP_MAC_KEY2     0x05683fbc
 219 #define MP_MAC_KEY3     0x3634fba4
 220 #define UNLOCK_MAC      0x00000008
 221         writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
 222         writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
 223         writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
 224         writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
 225         writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_USB_OHCI_NEW
 230 static void at91cap9_uhp_hw_init(void)
 231 {
 232         /* Unlock USB OHCI, 3 2 0 1 sequence */
 233 #define MP_OHCI_KEY0    0x896c11ca
 234 #define MP_OHCI_KEY1    0x68ebca21
 235 #define MP_OHCI_KEY2    0x4823efbc
 236 #define MP_OHCI_KEY3    0x8651aae4
 237 #define UNLOCK_OHCI     0x00000010
 238         writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
 239         writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
 240         writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
 241         writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
 242         writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_LCD
 247 vidinfo_t panel_info = {
 248         vl_col:         240,
 249         vl_row:         320,
 250         vl_clk:         4965000,
 251         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 252                         ATMEL_LCDC_INVFRAME_INVERTED,
 253         vl_bpix:        3,
 254         vl_tft:         1,
 255         vl_hsync_len:   5,
 256         vl_left_margin: 1,
 257         vl_right_margin:33,
 258         vl_vsync_len:   1,
 259         vl_upper_margin:1,
 260         vl_lower_margin:0,
 261         mmio:           AT91CAP9_LCDC_BASE,
 262 };
 263
 264 void lcd_enable(void)
 265 {
 266         at91_set_gpio_value(AT91_PIN_PC0, 0);  /* power up */
 267 }
 268
 269 void lcd_disable(void)
 270 {
 271         at91_set_gpio_value(AT91_PIN_PC0, 1);  /* power down */
 272 }
 273
 274 static void at91cap9_lcd_hw_init(void)
 275 {
 276         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 277         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 278         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 279         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 280         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 281         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 282         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 283         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 284         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 285         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 286         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 287         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 288         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 289         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 290         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 291         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 292         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 293         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 294         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 295         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
 296         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 297         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 298
 299         at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
 300
 301         gd->fb_base = 0;
 302 }
 303
 304 #ifdef CONFIG_LCD_INFO
 305 #include <nand.h>
 306 #include <version.h>
 307
 308 void lcd_show_board_info(void)
 309 {
 310         ulong dram_size, nand_size;
 311         int i;
 312         char temp[32];
 313
 314         lcd_printf ("%s\n", U_BOOT_VERSION);
 315         lcd_printf ("(C) 2008 ATMEL Corp\n");
 316         lcd_printf ("at91support@atmel.com\n");
 317         lcd_printf ("%s CPU at %s MHz\n",
 318                 AT91_CPU_NAME,
 319                 strmhz(temp, AT91_CPU_CLOCK));
 320
 321         dram_size = 0;
 322         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 323                 dram_size += gd->bd->bi_dram[i].size;
 324         nand_size = 0;
 325         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 326                 nand_size += nand_info[i].size;
 327         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 328                 dram_size >> 20,
 329                 nand_size >> 20 );
 330 }
 331 #endif /* CONFIG_LCD_INFO */
 332 #endif
 333
 334 int board_init(void)
 335 {
 336         /* Enable Ctrlc */
 337         console_init_f();
 338
 339         /* arch number of AT91CAP9ADK-Board */
 340         gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
 341         /* adress of boot parameters */
 342         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 343
 344         at91_serial_hw_init();
 345         at91cap9_slowclock_hw_init();
 346         at91cap9_nor_hw_init();
 347 #ifdef CONFIG_CMD_NAND
 348         at91cap9_nand_hw_init();
 349 #endif
 350 #ifdef CONFIG_HAS_DATAFLASH
 351         at91cap9_spi_hw_init();
 352 #endif
 353 #ifdef CONFIG_MACB
 354         at91cap9_macb_hw_init();
 355 #endif
 356 #ifdef CONFIG_USB_OHCI_NEW
 357         at91cap9_uhp_hw_init();
 358 #endif
 359 #ifdef CONFIG_LCD
 360         at91cap9_lcd_hw_init();
 361 #endif
 362         return 0;
 363 }
 364
 365 int dram_init(void)
 366 {
 367         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 368         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 369         return 0;
 370 }
 371
 372 #ifdef CONFIG_RESET_PHY_R
 373 void reset_phy(void)
 374 {
 375 #ifdef CONFIG_MACB
 376         /*
 377          * Initialize ethernet HW addr prior to starting Linux,
 378          * needed for nfsroot
 379          */
 380         eth_init(gd->bd);
 381 #endif
 382 }
 383 #endif
 384
 385 int board_eth_init(bd_t *bis)
 386 {
 387         int rc = 0;
 388 #ifdef CONFIG_MACB
 389         rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);
 390 #endif
 391         return rc;
 392 }