2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91cap9.h>
27 #include <asm/arch/at91cap9_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/io.h>
33 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
37 #define MP_BLOCK_3_BASE 0xFDF00000
39 DECLARE_GLOBAL_DATA_PTR;
41 /* ------------------------------------------------------------------------- */
43 * Miscelaneous platform dependent initialisations
46 static void at91cap9_serial_hw_init(void)
49 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
50 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
51 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
55 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
56 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
57 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
61 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
62 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
63 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
66 #ifdef CONFIG_USART3 /* DBGU */
67 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
68 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
69 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
73 static void at91cap9_nor_hw_init(void)
77 /* Ensure EBI supply is 3.3V */
78 csa = at91_sys_read(AT91_MATRIX_EBICSA);
79 at91_sys_write(AT91_MATRIX_EBICSA,
80 csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
81 /* Configure SMC CS0 for parallel flash */
82 at91_sys_write(AT91_SMC_SETUP(0),
83 AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
84 AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
85 at91_sys_write(AT91_SMC_PULSE(0),
86 AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
87 AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
88 at91_sys_write(AT91_SMC_CYCLE(0),
89 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
90 at91_sys_write(AT91_SMC_MODE(0),
91 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
92 AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
93 AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
96 #ifdef CONFIG_CMD_NAND
97 static void at91cap9_nand_hw_init(void)
102 csa = at91_sys_read(AT91_MATRIX_EBICSA);
103 at91_sys_write(AT91_MATRIX_EBICSA,
104 csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
105 AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
107 /* Configure SMC CS3 for NAND/SmartMedia */
108 at91_sys_write(AT91_SMC_SETUP(3),
109 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
110 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
111 at91_sys_write(AT91_SMC_PULSE(3),
112 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
113 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
114 at91_sys_write(AT91_SMC_CYCLE(3),
115 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
116 at91_sys_write(AT91_SMC_MODE(3),
117 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
118 AT91_SMC_EXNWMODE_DISABLE |
119 #ifdef CFG_NAND_DBW_16
121 #else /* CFG_NAND_DBW_8 */
126 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
128 /* RDY/BSY is not connected */
130 /* Enable NandFlash */
131 at91_set_gpio_output(AT91_PIN_PD15, 1);
135 #ifdef CONFIG_HAS_DATAFLASH
136 static void at91cap9_spi_hw_init(void)
138 at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
140 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
141 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
142 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
145 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
150 static void at91cap9_macb_hw_init(void)
153 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
156 * Disable pull-up on:
157 * RXDV (PB22) => PHY normal mode (not Test mode)
158 * ERX0 (PB25) => PHY ADDR0
159 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
161 * PHY has internal pull-down
163 writel(pin_to_mask(AT91_PIN_PB22) |
164 pin_to_mask(AT91_PIN_PB25) |
165 pin_to_mask(AT91_PIN_PB26),
166 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
168 /* Need to reset PHY -> 500ms reset */
169 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
170 AT91_RSTC_ERSTL | (0x0D << 8) |
173 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
175 /* Wait for end hardware reset */
176 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
178 /* Re-enable pull-up */
179 writel(pin_to_mask(AT91_PIN_PB22) |
180 pin_to_mask(AT91_PIN_PB25) |
181 pin_to_mask(AT91_PIN_PB26),
182 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
184 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
185 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
186 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
187 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
188 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
189 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
190 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
191 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
192 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
193 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
196 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
197 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
198 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
199 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
200 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
201 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
202 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
203 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
205 /* Unlock EMAC, 3 0 2 1 sequence */
206 #define MP_MAC_KEY0 0x5969cb2a
207 #define MP_MAC_KEY1 0xb4a1872e
208 #define MP_MAC_KEY2 0x05683fbc
209 #define MP_MAC_KEY3 0x3634fba4
210 #define UNLOCK_MAC 0x00000008
211 writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
212 writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
213 writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
214 writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
215 writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
219 #ifdef CONFIG_USB_OHCI_NEW
220 static void at91cap9_uhp_hw_init(void)
222 /* Unlock USB OHCI, 3 2 0 1 sequence */
223 #define MP_OHCI_KEY0 0x896c11ca
224 #define MP_OHCI_KEY1 0x68ebca21
225 #define MP_OHCI_KEY2 0x4823efbc
226 #define MP_OHCI_KEY3 0x8651aae4
227 #define UNLOCK_OHCI 0x00000010
228 writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
229 writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
230 writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
231 writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
232 writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
241 /* arch number of AT91CAP9ADK-Board */
242 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
243 /* adress of boot parameters */
244 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
246 at91cap9_serial_hw_init();
247 at91cap9_nor_hw_init();
248 #ifdef CONFIG_CMD_NAND
249 at91cap9_nand_hw_init();
251 #ifdef CONFIG_HAS_DATAFLASH
252 at91cap9_spi_hw_init();
255 at91cap9_macb_hw_init();
257 #ifdef CONFIG_USB_OHCI_NEW
258 at91cap9_uhp_hw_init();
265 gd->bd->bi_dram[0].start = PHYS_SDRAM;
266 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
270 #ifdef CONFIG_RESET_PHY_R
275 * Initialize ethernet HW addr prior to starting Linux,