2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91cap9.h>
27 #include <asm/arch/at91cap9_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/clk.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/io.h>
35 #include <asm/arch/hardware.h>
37 #include <atmel_lcdc.h>
38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
43 #define MP_BLOCK_3_BASE 0xFDF00000
45 DECLARE_GLOBAL_DATA_PTR;
47 /* ------------------------------------------------------------------------- */
49 * Miscelaneous platform dependent initialisations
52 static void at91cap9_slowclock_hw_init(void)
55 * On AT91CAP9 revC CPUs, the slow clock can be based on an
56 * internal impreciseRC oscillator or an external 32kHz oscillator.
57 * Switch to the latter.
59 #define ARCH_ID_AT91CAP9_REVB 0x399
60 #define ARCH_ID_AT91CAP9_REVC 0x601
61 if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
62 unsigned i, tmp = at91_sys_read(AT91_SCKCR);
63 if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
64 extern void timer_init(void);
66 tmp |= AT91CAP9_SCKCR_OSC32EN;
67 at91_sys_write(AT91_SCKCR, tmp);
68 for (i = 0; i < 1200; i++)
70 tmp |= AT91CAP9_SCKCR_OSCSEL_32;
71 at91_sys_write(AT91_SCKCR, tmp);
73 tmp &= ~AT91CAP9_SCKCR_RCEN;
74 at91_sys_write(AT91_SCKCR, tmp);
79 static void at91cap9_nor_hw_init(void)
83 /* Ensure EBI supply is 3.3V */
84 csa = at91_sys_read(AT91_MATRIX_EBICSA);
85 at91_sys_write(AT91_MATRIX_EBICSA,
86 csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
87 /* Configure SMC CS0 for parallel flash */
88 at91_sys_write(AT91_SMC_SETUP(0),
89 AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
90 AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
91 at91_sys_write(AT91_SMC_PULSE(0),
92 AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
93 AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
94 at91_sys_write(AT91_SMC_CYCLE(0),
95 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
96 at91_sys_write(AT91_SMC_MODE(0),
97 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
98 AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
99 AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
102 #ifdef CONFIG_CMD_NAND
103 static void at91cap9_nand_hw_init(void)
108 csa = at91_sys_read(AT91_MATRIX_EBICSA);
109 at91_sys_write(AT91_MATRIX_EBICSA,
110 csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
111 AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
113 /* Configure SMC CS3 for NAND/SmartMedia */
114 at91_sys_write(AT91_SMC_SETUP(3),
115 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
116 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
117 at91_sys_write(AT91_SMC_PULSE(3),
118 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
119 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
120 at91_sys_write(AT91_SMC_CYCLE(3),
121 AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
122 at91_sys_write(AT91_SMC_MODE(3),
123 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
124 AT91_SMC_EXNWMODE_DISABLE |
125 #ifdef CONFIG_SYS_NAND_DBW_16
127 #else /* CONFIG_SYS_NAND_DBW_8 */
132 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
134 /* RDY/BSY is not connected */
136 /* Enable NandFlash */
137 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
142 static void at91cap9_macb_hw_init(void)
145 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
148 * Disable pull-up on:
149 * RXDV (PB22) => PHY normal mode (not Test mode)
150 * ERX0 (PB25) => PHY ADDR0
151 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
153 * PHY has internal pull-down
155 writel(pin_to_mask(AT91_PIN_PB22) |
156 pin_to_mask(AT91_PIN_PB25) |
157 pin_to_mask(AT91_PIN_PB26),
158 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
160 /* Need to reset PHY -> 500ms reset */
161 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
162 (AT91_RSTC_ERSTL & (0x0D << 8)) |
165 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
167 /* Wait for end hardware reset */
168 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
170 /* Restore NRST value */
171 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
172 (AT91_RSTC_ERSTL & (0x0 << 8)) |
175 /* Re-enable pull-up */
176 writel(pin_to_mask(AT91_PIN_PB22) |
177 pin_to_mask(AT91_PIN_PB25) |
178 pin_to_mask(AT91_PIN_PB26),
179 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
183 /* Unlock EMAC, 3 0 2 1 sequence */
184 #define MP_MAC_KEY0 0x5969cb2a
185 #define MP_MAC_KEY1 0xb4a1872e
186 #define MP_MAC_KEY2 0x05683fbc
187 #define MP_MAC_KEY3 0x3634fba4
188 #define UNLOCK_MAC 0x00000008
189 writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
190 writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
191 writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
192 writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
193 writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
197 #ifdef CONFIG_USB_OHCI_NEW
198 static void at91cap9_uhp_hw_init(void)
200 /* Unlock USB OHCI, 3 2 0 1 sequence */
201 #define MP_OHCI_KEY0 0x896c11ca
202 #define MP_OHCI_KEY1 0x68ebca21
203 #define MP_OHCI_KEY2 0x4823efbc
204 #define MP_OHCI_KEY3 0x8651aae4
205 #define UNLOCK_OHCI 0x00000010
206 writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
207 writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
208 writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
209 writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
210 writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
215 vidinfo_t panel_info = {
219 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
220 ATMEL_LCDC_INVFRAME_INVERTED,
229 mmio: AT91CAP9_LCDC_BASE,
232 void lcd_enable(void)
234 at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */
237 void lcd_disable(void)
239 at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */
242 static void at91cap9_lcd_hw_init(void)
244 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
245 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
246 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
247 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
248 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
249 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
250 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
251 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
252 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
253 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
254 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
255 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
256 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
257 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
258 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
259 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
260 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
261 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
262 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
263 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
264 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
265 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
267 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC);
272 #ifdef CONFIG_LCD_INFO
276 void lcd_show_board_info(void)
278 ulong dram_size, nand_size;
282 lcd_printf ("%s\n", U_BOOT_VERSION);
283 lcd_printf ("(C) 2008 ATMEL Corp\n");
284 lcd_printf ("at91support@atmel.com\n");
285 lcd_printf ("%s CPU at %s MHz\n",
287 strmhz(temp, get_cpu_clk_rate()));
290 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
291 dram_size += gd->bd->bi_dram[i].size;
293 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
294 nand_size += nand_info[i].size;
295 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
299 #endif /* CONFIG_LCD_INFO */
307 /* arch number of AT91CAP9ADK-Board */
308 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
309 /* adress of boot parameters */
310 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
312 at91_serial_hw_init();
313 at91cap9_slowclock_hw_init();
314 at91cap9_nor_hw_init();
315 #ifdef CONFIG_CMD_NAND
316 at91cap9_nand_hw_init();
318 #ifdef CONFIG_HAS_DATAFLASH
319 at91_spi0_hw_init(1 << 0);
322 at91cap9_macb_hw_init();
324 #ifdef CONFIG_USB_OHCI_NEW
325 at91cap9_uhp_hw_init();
328 at91cap9_lcd_hw_init();
335 gd->bd->bi_dram[0].start = PHYS_SDRAM;
336 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
340 #ifdef CONFIG_RESET_PHY_R
345 * Initialize ethernet HW addr prior to starting Linux,
353 int board_eth_init(bd_t *bis)
357 rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00);