git.sur5r.net Git - u-boot/blob - board/atmel/at91cap9adk/at91cap9adk.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop <at> leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/AT91CAP9.h>
  27
  28 #define MP_BLOCK_3_BASE 0xFDF00000
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 /* ------------------------------------------------------------------------- */
  33 /*
  34  * Miscelaneous platform dependent initialisations
  35  */
  36
  37 static void at91cap9_serial_hw_init(void)
  38 {
  39 #ifdef CONFIG_USART0
  40         AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
  41         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
  42 #endif
  43
  44 #ifdef CONFIG_USART1
  45         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
  46         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
  47 #endif
  48
  49 #ifdef CONFIG_USART2
  50         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
  51         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
  52 #endif
  53
  54 #ifdef CONFIG_USART3    /* DBGU */
  55         AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
  56         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
  57 #endif
  58
  59
  60 }
  61
  62 static void at91cap9_nor_hw_init(void)
  63 {
  64         /* Ensure EBI supply is 3.3V */
  65         AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
  66
  67         /* Configure SMC CS0 for parallel flash */
  68         AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
  69                                      AT91C_FLASH_NCS_WR_SETUP |
  70                                      AT91C_FLASH_NRD_SETUP |
  71                                      AT91C_FLASH_NCS_RD_SETUP;
  72
  73         AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
  74                                      AT91C_FLASH_NCS_WR_PULSE |
  75                                      AT91C_FLASH_NRD_PULSE |
  76                                      AT91C_FLASH_NCS_RD_PULSE;
  77
  78         AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
  79                                      AT91C_FLASH_NRD_CYCLE;
  80
  81         AT91C_BASE_SMC->SMC_CTRL0 =  AT91C_SMC_READMODE |
  82                                      AT91C_SMC_WRITEMODE |
  83                                      AT91C_SMC_NWAITM_NWAIT_DISABLE |
  84                                      AT91C_SMC_BAT_BYTE_WRITE |
  85                                      AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
  86                                      (AT91C_SMC_TDF & (1 << 16));
  87 }
  88
  89 #ifdef CONFIG_CMD_NAND
  90 static void at91cap9_nand_hw_init(void)
  91 {
  92         /* Enable CS3 */
  93         AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
  94
  95         /* Configure SMC CS3 for NAND/SmartMedia */
  96         AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
  97                                      AT91C_SM_NCS_WR_SETUP |
  98                                      AT91C_SM_NRD_SETUP |
  99                                      AT91C_SM_NCS_RD_SETUP;
 100
 101         AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
 102                                      AT91C_SM_NCS_WR_PULSE |
 103                                      AT91C_SM_NRD_PULSE |
 104                                      AT91C_SM_NCS_RD_PULSE;
 105
 106         AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
 107                                      AT91C_SM_NRD_CYCLE;
 108
 109         AT91C_BASE_SMC->SMC_CTRL3 =  AT91C_SMC_READMODE |
 110                                      AT91C_SMC_WRITEMODE |
 111                                      AT91C_SMC_NWAITM_NWAIT_DISABLE |
 112                                      AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
 113                                      AT91C_SM_TDF;
 114
 115         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
 116
 117         /* RDY/BSY is not connected */
 118
 119         /* Enable NandFlash */
 120         AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
 121         AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_HAS_DATAFLASH
 126 static void at91cap9_spi_hw_init(void)
 127 {
 128         AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
 129                                    AT91C_PD1_SPI0_NPCS3D;
 130         AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
 131                                    AT91C_PD1_SPI0_NPCS3D;
 132
 133         AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
 134         AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
 135                                    AT91C_PA1_SPI0_MOSI |
 136                                    AT91C_PA0_SPI0_MISO |
 137                                    AT91C_PA3_SPI0_NPCS1 |
 138                                    AT91C_PA5_SPI0_NPCS0 |
 139                                    AT91C_PA2_SPI0_SPCK;
 140         AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
 141                                    AT91C_PA4_SPI0_NPCS2A |
 142                                    AT91C_PA1_SPI0_MOSI |
 143                                    AT91C_PA0_SPI0_MISO |
 144                                    AT91C_PA3_SPI0_NPCS1 |
 145                                    AT91C_PA5_SPI0_NPCS0 |
 146                                    AT91C_PA2_SPI0_SPCK;
 147
 148         /* Enable Clock */
 149         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_MACB
 154 static void at91cap9_macb_hw_init(void)
 155 {
 156         unsigned int gpio;
 157
 158         /* Enable clock */
 159         AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
 160
 161         /*
 162          * Disable pull-up on:
 163          *      RXDV (PB22) => PHY normal mode (not Test mode)
 164          *      ERX0 (PB25) => PHY ADDR0
 165          *      ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
 166          *
 167          * PHY has internal pull-down
 168          */
 169         AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
 170                                      AT91C_PB25_E_RX0 |
 171                                      AT91C_PB26_E_RX1;
 172
 173         /* Need to reset PHY -> 500ms reset */
 174         AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
 175                                     (AT91C_RSTC_ERSTL & (0x0D << 8)) |
 176                                     AT91C_RSTC_URSTEN;
 177         AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
 178                                     AT91C_RSTC_EXTRST;
 179
 180         /* Wait for end hardware reset */
 181         while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
 182
 183         /* Re-enable pull-up */
 184         AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
 185                                      AT91C_PB25_E_RX0 |
 186                                      AT91C_PB26_E_RX1;
 187
 188 #ifdef CONFIG_RMII
 189         gpio =  AT91C_PB30_E_MDIO |
 190                 AT91C_PB29_E_MDC  |
 191                 AT91C_PB21_E_TXCK |
 192                 AT91C_PB27_E_RXER |
 193                 AT91C_PB25_E_RX0  |
 194                 AT91C_PB22_E_RXDV |
 195                 AT91C_PB26_E_RX1  |
 196                 AT91C_PB28_E_TXEN |
 197                 AT91C_PB23_E_TX0  |
 198                 AT91C_PB24_E_TX1;
 199         AT91C_BASE_PIOB->PIO_ASR = gpio;
 200         AT91C_BASE_PIOB->PIO_BSR = 0;
 201         AT91C_BASE_PIOB->PIO_PDR = gpio;
 202 #else
 203 #error AT91CAP9A-DK works only in RMII mode
 204 #endif
 205
 206         /* Unlock EMAC, 3 0 2 1 sequence */
 207 #define MP_MAC_KEY0     0x5969cb2a
 208 #define MP_MAC_KEY1     0xb4a1872e
 209 #define MP_MAC_KEY2     0x05683fbc
 210 #define MP_MAC_KEY3     0x3634fba4
 211 #define UNLOCK_MAC      0x00000008
 212         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
 213         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
 214         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
 215         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
 216         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
 217 }
 218 #endif
 219
 220 #ifdef CONFIG_USB_OHCI_NEW
 221 static void at91cap9_uhp_hw_init(void)
 222 {
 223         /* Unlock USB OHCI, 3 2 0 1 sequence */
 224 #define MP_OHCI_KEY0    0x896c11ca
 225 #define MP_OHCI_KEY1    0x68ebca21
 226 #define MP_OHCI_KEY2    0x4823efbc
 227 #define MP_OHCI_KEY3    0x8651aae4
 228 #define UNLOCK_OHCI     0x00000010
 229         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
 230         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
 231         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
 232         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
 233         *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
 234 }
 235 #endif
 236
 237 int board_init(void)
 238 {
 239         /* Enable Ctrlc */
 240         console_init_f();
 241
 242         /* arch number of AT91CAP9ADK-Board */
 243         gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
 244         /* adress of boot parameters */
 245         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 246
 247         at91cap9_serial_hw_init();
 248         at91cap9_nor_hw_init();
 249 #ifdef CONFIG_CMD_NAND
 250         at91cap9_nand_hw_init();
 251 #endif
 252 #ifdef CONFIG_HAS_DATAFLASH
 253         at91cap9_spi_hw_init();
 254 #endif
 255 #ifdef CONFIG_MACB
 256         at91cap9_macb_hw_init();
 257 #endif
 258 #ifdef CONFIG_USB_OHCI_NEW
 259         at91cap9_uhp_hw_init();
 260 #endif
 261
 262         return 0;
 263 }
 264
 265 int dram_init(void)
 266 {
 267         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 268         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 269         return 0;
 270 }
 271
 272 #ifdef CONFIG_RESET_PHY_R
 273 void reset_phy(void)
 274 {
 275 #ifdef CONFIG_MACB
 276         /*
 277          * Initialize ethernet HW addr prior to starting Linux,
 278          * needed for nfsroot
 279          */
 280         eth_init(gd->bd);
 281 #endif
 282 }
 283 #endif