2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop <at> leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/AT91CAP9.h>
28 #define MP_BLOCK_3_BASE 0xFDF00000
30 DECLARE_GLOBAL_DATA_PTR;
32 /* ------------------------------------------------------------------------- */
34 * Miscelaneous platform dependent initialisations
37 static void at91cap9_serial_hw_init(void)
40 AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
41 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
45 AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
46 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
50 AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
51 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
54 #ifdef CONFIG_USART3 /* DBGU */
55 AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
56 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
62 static void at91cap9_nor_hw_init(void)
64 /* Ensure EBI supply is 3.3V */
65 AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
67 /* Configure SMC CS0 for parallel flash */
68 AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
69 AT91C_FLASH_NCS_WR_SETUP |
70 AT91C_FLASH_NRD_SETUP |
71 AT91C_FLASH_NCS_RD_SETUP;
73 AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
74 AT91C_FLASH_NCS_WR_PULSE |
75 AT91C_FLASH_NRD_PULSE |
76 AT91C_FLASH_NCS_RD_PULSE;
78 AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
79 AT91C_FLASH_NRD_CYCLE;
81 AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE |
83 AT91C_SMC_NWAITM_NWAIT_DISABLE |
84 AT91C_SMC_BAT_BYTE_WRITE |
85 AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
86 (AT91C_SMC_TDF & (1 << 16));
89 #ifdef CONFIG_CMD_NAND
90 static void at91cap9_nand_hw_init(void)
93 AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
95 /* Configure SMC CS3 for NAND/SmartMedia */
96 AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
97 AT91C_SM_NCS_WR_SETUP |
99 AT91C_SM_NCS_RD_SETUP;
101 AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
102 AT91C_SM_NCS_WR_PULSE |
104 AT91C_SM_NCS_RD_PULSE;
106 AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
109 AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE |
110 AT91C_SMC_WRITEMODE |
111 AT91C_SMC_NWAITM_NWAIT_DISABLE |
112 AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
115 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
117 /* RDY/BSY is not connected */
119 /* Enable NandFlash */
120 AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
121 AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
125 #ifdef CONFIG_HAS_DATAFLASH
126 static void at91cap9_spi_hw_init(void)
128 AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
129 AT91C_PD1_SPI0_NPCS3D;
130 AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
131 AT91C_PD1_SPI0_NPCS3D;
133 AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
134 AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
135 AT91C_PA1_SPI0_MOSI |
136 AT91C_PA0_SPI0_MISO |
137 AT91C_PA3_SPI0_NPCS1 |
138 AT91C_PA5_SPI0_NPCS0 |
140 AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
141 AT91C_PA4_SPI0_NPCS2A |
142 AT91C_PA1_SPI0_MOSI |
143 AT91C_PA0_SPI0_MISO |
144 AT91C_PA3_SPI0_NPCS1 |
145 AT91C_PA5_SPI0_NPCS0 |
149 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
154 static void at91cap9_macb_hw_init(void)
159 AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
162 * Disable pull-up on:
163 * RXDV (PB22) => PHY normal mode (not Test mode)
164 * ERX0 (PB25) => PHY ADDR0
165 * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0
167 * PHY has internal pull-down
169 AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
173 /* Need to reset PHY -> 500ms reset */
174 AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
175 (AT91C_RSTC_ERSTL & (0x0D << 8)) |
177 AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
180 /* Wait for end hardware reset */
181 while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
183 /* Re-enable pull-up */
184 AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
189 gpio = AT91C_PB30_E_MDIO |
199 AT91C_BASE_PIOB->PIO_ASR = gpio;
200 AT91C_BASE_PIOB->PIO_BSR = 0;
201 AT91C_BASE_PIOB->PIO_PDR = gpio;
203 #error AT91CAP9A-DK works only in RMII mode
206 /* Unlock EMAC, 3 0 2 1 sequence */
207 #define MP_MAC_KEY0 0x5969cb2a
208 #define MP_MAC_KEY1 0xb4a1872e
209 #define MP_MAC_KEY2 0x05683fbc
210 #define MP_MAC_KEY3 0x3634fba4
211 #define UNLOCK_MAC 0x00000008
212 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
213 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
214 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
215 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
216 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
220 #ifdef CONFIG_USB_OHCI_NEW
221 static void at91cap9_uhp_hw_init(void)
223 /* Unlock USB OHCI, 3 2 0 1 sequence */
224 #define MP_OHCI_KEY0 0x896c11ca
225 #define MP_OHCI_KEY1 0x68ebca21
226 #define MP_OHCI_KEY2 0x4823efbc
227 #define MP_OHCI_KEY3 0x8651aae4
228 #define UNLOCK_OHCI 0x00000010
229 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
230 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
231 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
232 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
233 *((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
242 /* arch number of AT91CAP9ADK-Board */
243 gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK;
244 /* adress of boot parameters */
245 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
247 at91cap9_serial_hw_init();
248 at91cap9_nor_hw_init();
249 #ifdef CONFIG_CMD_NAND
250 at91cap9_nand_hw_init();
252 #ifdef CONFIG_HAS_DATAFLASH
253 at91cap9_spi_hw_init();
256 at91cap9_macb_hw_init();
258 #ifdef CONFIG_USB_OHCI_NEW
259 at91cap9_uhp_hw_init();
267 gd->bd->bi_dram[0].start = PHYS_SDRAM;
268 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
272 #ifdef CONFIG_RESET_PHY_R
277 * Initialize ethernet HW addr prior to starting Linux,