2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/at91sam9260_matrix.h>
12 #include <asm/arch/at91sam9_smc.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/gpio.h>
16 #include <atmel_mci.h>
18 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23 DECLARE_GLOBAL_DATA_PTR;
25 /* ------------------------------------------------------------------------- */
27 * Miscelaneous platform dependent initialisations
30 #ifdef CONFIG_CMD_NAND
31 static void at91sam9260ek_nand_hw_init(void)
33 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
34 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37 /* Assign CS3 to NAND/SmartMedia Interface */
38 csa = readl(&matrix->ebicsa);
39 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
40 writel(csa, &matrix->ebicsa);
42 /* Configure SMC CS3 for NAND/SmartMedia */
43 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
44 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
46 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
47 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
49 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
51 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
52 AT91_SMC_MODE_EXNW_DISABLE |
53 #ifdef CONFIG_SYS_NAND_DBW_16
54 AT91_SMC_MODE_DBW_16 |
55 #else /* CONFIG_SYS_NAND_DBW_8 */
58 AT91_SMC_MODE_TDF_CYCLE(2),
61 /* Configure RDY/BSY */
62 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
64 /* Enable NandFlash */
65 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
71 static void at91sam9260ek_macb_hw_init(void)
73 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
75 at91_periph_clk_enable(ATMEL_ID_EMAC0);
79 * RXDV (PA17) => PHY normal mode (not Test mode)
80 * ERX0 (PA14) => PHY ADDR0
81 * ERX1 (PA15) => PHY ADDR1
82 * ERX2 (PA25) => PHY ADDR2
83 * ERX3 (PA26) => PHY ADDR3
84 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
86 * PHY has internal pull-down
88 writel(pin_to_mask(AT91_PIN_PA14) |
89 pin_to_mask(AT91_PIN_PA15) |
90 pin_to_mask(AT91_PIN_PA17) |
91 pin_to_mask(AT91_PIN_PA25) |
92 pin_to_mask(AT91_PIN_PA26) |
93 pin_to_mask(AT91_PIN_PA28),
98 /* Re-enable pull-up */
99 writel(pin_to_mask(AT91_PIN_PA14) |
100 pin_to_mask(AT91_PIN_PA15) |
101 pin_to_mask(AT91_PIN_PA17) |
102 pin_to_mask(AT91_PIN_PA25) |
103 pin_to_mask(AT91_PIN_PA26) |
104 pin_to_mask(AT91_PIN_PA28),
107 /* Initialize EMAC=MACB hardware */
112 #ifdef CONFIG_GENERIC_ATMEL_MCI
113 int board_mmc_init(bd_t *bd)
117 return atmel_mci_init((void *)ATMEL_BASE_MCI);
121 int board_early_init_f(void)
123 at91_periph_clk_enable(ATMEL_ID_PIOA);
124 at91_periph_clk_enable(ATMEL_ID_PIOB);
125 at91_periph_clk_enable(ATMEL_ID_PIOC);
132 /* adress of boot parameters */
133 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
135 at91_seriald_hw_init();
136 #ifdef CONFIG_CMD_NAND
137 at91sam9260ek_nand_hw_init();
139 #ifdef CONFIG_HAS_DATAFLASH
140 at91_spi0_hw_init((1 << 0) | (1 << 1));
143 at91sam9260ek_macb_hw_init();
151 gd->ram_size = get_ram_size(
152 (void *)CONFIG_SYS_SDRAM_BASE,
153 CONFIG_SYS_SDRAM_SIZE);
157 #ifdef CONFIG_RESET_PHY_R
163 int board_eth_init(bd_t *bis)
167 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);