2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
11 #include <asm/arch/at91sam9263.h>
12 #include <asm/arch/at91sam9_smc.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/at91_matrix.h>
15 #include <asm/arch/at91_pio.h>
16 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/hardware.h>
21 #include <atmel_lcdc.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
26 #include <atmel_mci.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* ------------------------------------------------------------------------- */
32 * Miscelaneous platform dependent initialisations
35 #ifdef CONFIG_CMD_NAND
36 static void at91sam9263ek_nand_hw_init(void)
39 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
40 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
43 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
44 writel(csa, &matrix->csa[0]);
48 /* Configure SMC CS3 for NAND/SmartMedia */
49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_TDF_CYCLE(2),
69 at91_periph_clk_enable(ATMEL_ID_PIOA);
70 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
72 /* Configure RDY/BSY */
73 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
75 /* Enable NandFlash */
76 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
81 static void at91sam9263ek_macb_hw_init(void)
83 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
85 at91_periph_clk_enable(ATMEL_ID_EMAC);
89 * RXDV (PC25) => PHY normal mode (not Test mode)
90 * ERX0 (PE25) => PHY ADDR0
91 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
93 * PHY has internal pull-down
95 writel(1 << 25, &pio->pioc.pudr);
96 writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
100 /* Re-enable pull-up */
101 writel(1 << 25, &pio->pioc.puer);
102 writel((1 << 25) | (1 <<26), &pio->pioe.puer);
109 vidinfo_t panel_info = {
113 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
114 ATMEL_LCDC_INVFRAME_INVERTED,
119 .vl_right_margin = 33,
121 .vl_upper_margin = 1,
122 .vl_lower_margin = 0,
123 .mmio = ATMEL_BASE_LCDC,
126 void lcd_enable(void)
128 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
131 void lcd_disable(void)
133 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
136 static void at91sam9263ek_lcd_hw_init(void)
138 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
139 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
140 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
141 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
142 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
143 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
144 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
145 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
146 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
147 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
148 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
149 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
150 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
151 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
152 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
153 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
154 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
155 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
156 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
157 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
158 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
159 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
161 at91_periph_clk_enable(ATMEL_ID_LCDC);
162 gd->fb_base = ATMEL_BASE_SRAM0;
165 #ifdef CONFIG_LCD_INFO
169 #ifndef CONFIG_SYS_NO_FLASH
170 extern flash_info_t flash_info[];
173 void lcd_show_board_info(void)
175 ulong dram_size, nand_size;
176 #ifndef CONFIG_SYS_NO_FLASH
182 lcd_printf ("%s\n", U_BOOT_VERSION);
183 lcd_printf ("(C) 2008 ATMEL Corp\n");
184 lcd_printf ("at91support@atmel.com\n");
185 lcd_printf ("%s CPU at %s MHz\n",
187 strmhz(temp, get_cpu_clk_rate()));
190 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
191 dram_size += gd->bd->bi_dram[i].size;
193 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
194 nand_size += nand_info[i].size;
195 #ifndef CONFIG_SYS_NO_FLASH
197 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
198 flash_size += flash_info[i].size;
200 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
203 #ifndef CONFIG_SYS_NO_FLASH
204 lcd_printf (",\n %ld MB NOR",
209 #endif /* CONFIG_LCD_INFO */
212 #ifdef CONFIG_GENERIC_ATMEL_MCI
213 int board_mmc_init(bd_t *bd)
217 return atmel_mci_init((void *)ATMEL_BASE_MCI1);
221 int board_early_init_f(void)
223 at91_periph_clk_enable(ATMEL_ID_PIOA);
224 at91_periph_clk_enable(ATMEL_ID_PIOB);
225 at91_periph_clk_enable(ATMEL_ID_PIOCDE);
227 at91_seriald_hw_init();
233 /* arch number of AT91SAM9263EK-Board */
234 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
235 /* adress of boot parameters */
236 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
238 #ifdef CONFIG_CMD_NAND
239 at91sam9263ek_nand_hw_init();
241 #ifdef CONFIG_HAS_DATAFLASH
242 at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
243 at91_spi0_hw_init(1 << 0);
246 at91sam9263ek_macb_hw_init();
248 #ifdef CONFIG_USB_OHCI_NEW
252 at91sam9263ek_lcd_hw_init();
259 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
260 CONFIG_SYS_SDRAM_SIZE);
265 #ifdef CONFIG_RESET_PHY_R
271 int board_eth_init(bd_t *bis)
275 rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);