2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/arch/at91_rstc.h>
15 #include <asm/arch/at91_pio.h>
16 #include <asm/arch/clk.h>
18 #include <atmel_hlcdc.h>
19 #include <atmel_mci.h>
22 #ifdef CONFIG_LCD_INFO
27 DECLARE_GLOBAL_DATA_PTR;
29 /* ------------------------------------------------------------------------- */
31 * Miscelaneous platform dependent initialisations
33 #ifdef CONFIG_NAND_ATMEL
34 static void at91sam9n12ek_nand_hw_init(void)
36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
40 /* Assign CS3 to NAND/SmartMedia Interface */
41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 /* Configure databus */
44 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
45 /* Configure IO drive */
46 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
48 writel(csa, &matrix->ebicsa);
50 /* Configure SMC CS3 for NAND/SmartMedia */
51 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
52 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
55 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_TDF_CYCLE(1),
69 /* Configure RDY/BSY pin */
70 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
72 /* Configure ENABLE pin for NandFlash */
73 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
75 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
76 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
77 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
78 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
83 vidinfo_t panel_info = {
92 .vl_right_margin = 43,
95 .vl_lower_margin = 12,
96 .mmio = ATMEL_BASE_LCDC,
101 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
104 void lcd_disable(void)
106 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
109 #ifdef CONFIG_LCD_INFO
110 void lcd_show_board_info(void)
112 ulong dram_size, nand_size;
116 lcd_printf("%s\n", U_BOOT_VERSION);
117 lcd_printf("ATMEL Corp\n");
118 lcd_printf("at91@atmel.com\n");
119 lcd_printf("%s CPU at %s MHz\n",
121 strmhz(temp, get_cpu_clk_rate()));
124 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
125 dram_size += gd->bd->bi_dram[i].size;
127 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
128 nand_size += nand_info[i].size;
129 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
133 #endif /* CONFIG_LCD_INFO */
134 #endif /* CONFIG_LCD */
136 /* SPI chip select control */
137 #ifdef CONFIG_ATMEL_SPI
139 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
141 return bus == 0 && cs < 2;
144 void spi_cs_activate(struct spi_slave *slave)
148 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
151 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
156 void spi_cs_deactivate(struct spi_slave *slave)
160 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
163 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
167 #endif /* CONFIG_ATMEL_SPI */
169 #ifdef CONFIG_GENERIC_ATMEL_MCI
170 int board_mmc_init(bd_t *bd)
174 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
178 #ifdef CONFIG_KS8851_MLL
179 void at91sam9n12ek_ks8851_hw_init(void)
181 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
183 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
184 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
186 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
187 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
189 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
191 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
192 AT91_SMC_MODE_EXNW_DISABLE |
193 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
194 AT91_SMC_MODE_TDF_CYCLE(1),
197 /* Configure NCS2 PIN */
198 at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
202 #ifdef CONFIG_USB_ATMEL
203 void at91sam9n12ek_usb_hw_init(void)
205 at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
209 int board_early_init_f(void)
211 /* Enable clocks for all PIOs */
212 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
213 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
215 at91_seriald_hw_init();
221 /* adress of boot parameters */
222 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
224 #ifdef CONFIG_NAND_ATMEL
225 at91sam9n12ek_nand_hw_init();
228 #ifdef CONFIG_ATMEL_SPI
229 at91_spi0_hw_init(1 << 0);
236 #ifdef CONFIG_KS8851_MLL
237 at91sam9n12ek_ks8851_hw_init();
240 #ifdef CONFIG_USB_ATMEL
241 at91sam9n12ek_usb_hw_init();
247 #ifdef CONFIG_KS8851_MLL
248 int board_eth_init(bd_t *bis)
250 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
256 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
257 CONFIG_SYS_SDRAM_SIZE);
261 #if defined(CONFIG_SPL_BUILD)
265 void at91_spl_board_init(void)
267 #ifdef CONFIG_SYS_USE_MMC
269 #elif CONFIG_SYS_USE_NANDFLASH
270 at91sam9n12ek_nand_hw_init();
271 #elif CONFIG_SYS_USE_SPIFLASH
272 at91_spi0_hw_init(1 << 4);
276 #include <asm/arch/atmel_mpddrc.h>
277 static void ddr2_conf(struct atmel_mpddr *ddr2)
279 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
281 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
282 ATMEL_MPDDRC_CR_NR_ROW_13 |
283 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
284 ATMEL_MPDDRC_CR_NB_8BANKS |
285 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
289 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
290 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
291 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
292 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
293 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
294 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
295 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
296 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
298 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
299 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
300 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
301 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
303 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
304 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
305 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
306 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
311 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
312 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
313 struct atmel_mpddr ddr2;
318 /* enable DDR2 clock */
319 writel(0x4, &pmc->scer);
321 /* Chip select 1 is for DDR2/SDRAM */
322 csa = readl(&matrix->ebicsa);
323 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
324 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
325 csa |= AT91_MATRIX_EBI_DBPD_OFF;
326 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
327 writel(csa, &matrix->ebicsa);
329 /* DDRAM2 Controller initialize */
330 ddr2_init(ATMEL_BASE_CS1, &ddr2);