2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/at91_pio.h>
15 #include <asm/arch/clk.h>
17 #include <atmel_hlcdc.h>
20 #ifdef CONFIG_LCD_INFO
25 DECLARE_GLOBAL_DATA_PTR;
27 /* ------------------------------------------------------------------------- */
29 * Miscelaneous platform dependent initialisations
31 #ifdef CONFIG_NAND_ATMEL
32 static void at91sam9n12ek_nand_hw_init(void)
34 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
35 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38 /* Assign CS3 to NAND/SmartMedia Interface */
39 csa = readl(&matrix->ebicsa);
40 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
41 /* Configure databus */
42 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
43 /* Configure IO drive */
44 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
46 writel(csa, &matrix->ebicsa);
48 /* Configure SMC CS3 for NAND/SmartMedia */
49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
50 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
53 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
58 AT91_SMC_MODE_EXNW_DISABLE |
59 #ifdef CONFIG_SYS_NAND_DBW_16
60 AT91_SMC_MODE_DBW_16 |
61 #else /* CONFIG_SYS_NAND_DBW_8 */
64 AT91_SMC_MODE_TDF_CYCLE(1),
67 /* Configure RDY/BSY pin */
68 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
70 /* Configure ENABLE pin for NandFlash */
71 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
81 vidinfo_t panel_info = {
90 .vl_right_margin = 43,
93 .vl_lower_margin = 12,
94 .mmio = ATMEL_BASE_LCDC,
99 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
102 void lcd_disable(void)
104 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
107 #ifdef CONFIG_LCD_INFO
108 void lcd_show_board_info(void)
110 ulong dram_size, nand_size;
114 lcd_printf("%s\n", U_BOOT_VERSION);
115 lcd_printf("ATMEL Corp\n");
116 lcd_printf("at91@atmel.com\n");
117 lcd_printf("%s CPU at %s MHz\n",
119 strmhz(temp, get_cpu_clk_rate()));
122 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
123 dram_size += gd->bd->bi_dram[i].size;
125 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
126 nand_size += nand_info[i]->size;
127 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
131 #endif /* CONFIG_LCD_INFO */
132 #endif /* CONFIG_LCD */
134 #ifdef CONFIG_KS8851_MLL
135 void at91sam9n12ek_ks8851_hw_init(void)
137 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
139 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
140 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
142 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
143 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
145 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
147 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
148 AT91_SMC_MODE_EXNW_DISABLE |
149 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
150 AT91_SMC_MODE_TDF_CYCLE(1),
153 /* Configure NCS2 PIN */
154 at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
158 #ifdef CONFIG_USB_ATMEL
159 void at91sam9n12ek_usb_hw_init(void)
161 at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
165 int board_early_init_f(void)
172 /* adress of boot parameters */
173 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
175 #ifdef CONFIG_NAND_ATMEL
176 at91sam9n12ek_nand_hw_init();
183 #ifdef CONFIG_KS8851_MLL
184 at91sam9n12ek_ks8851_hw_init();
187 #ifdef CONFIG_USB_ATMEL
188 at91sam9n12ek_usb_hw_init();
194 #ifdef CONFIG_KS8851_MLL
195 int board_eth_init(bd_t *bis)
197 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
203 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
204 CONFIG_SYS_SDRAM_SIZE);
208 #if defined(CONFIG_SPL_BUILD)
212 void at91_spl_board_init(void)
214 #ifdef CONFIG_SYS_USE_MMC
216 #elif CONFIG_SYS_USE_NANDFLASH
217 at91sam9n12ek_nand_hw_init();
218 #elif CONFIG_SYS_USE_SPIFLASH
219 at91_spi0_hw_init(1 << 4);
223 #include <asm/arch/atmel_mpddrc.h>
224 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
226 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
228 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
229 ATMEL_MPDDRC_CR_NR_ROW_13 |
230 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
231 ATMEL_MPDDRC_CR_NB_8BANKS |
232 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
236 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
237 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
238 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
239 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
240 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
241 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
242 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
243 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
245 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
246 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
247 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
248 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
250 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
251 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
252 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
253 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
258 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
259 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
260 struct atmel_mpddrc_config ddr2;
265 /* enable DDR2 clock */
266 writel(AT91_PMC_DDR, &pmc->scer);
268 /* Chip select 1 is for DDR2/SDRAM */
269 csa = readl(&matrix->ebicsa);
270 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
271 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
272 csa |= AT91_MATRIX_EBI_DBPD_OFF;
273 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
274 writel(csa, &matrix->ebicsa);
276 /* DDRAM2 Controller initialize */
277 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);