2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91sam9x5_matrix.h>
27 #include <asm/arch/at91sam9_smc.h>
28 #include <asm/arch/at91_common.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/at91_pio.h>
32 #include <asm/arch/clk.h>
34 #include <atmel_hlcdc.h>
35 #include <atmel_mci.h>
38 #ifdef CONFIG_LCD_INFO
43 DECLARE_GLOBAL_DATA_PTR;
45 /* ------------------------------------------------------------------------- */
47 * Miscelaneous platform dependent initialisations
49 #ifdef CONFIG_NAND_ATMEL
50 static void at91sam9n12ek_nand_hw_init(void)
52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
56 /* Assign CS3 to NAND/SmartMedia Interface */
57 csa = readl(&matrix->ebicsa);
58 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
59 /* Configure databus */
60 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
61 /* Configure IO drive */
62 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
64 writel(csa, &matrix->ebicsa);
66 /* Configure SMC CS3 for NAND/SmartMedia */
67 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
68 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
71 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
73 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
75 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
76 AT91_SMC_MODE_EXNW_DISABLE |
77 #ifdef CONFIG_SYS_NAND_DBW_16
78 AT91_SMC_MODE_DBW_16 |
79 #else /* CONFIG_SYS_NAND_DBW_8 */
82 AT91_SMC_MODE_TDF_CYCLE(1),
85 /* Configure RDY/BSY pin */
86 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
88 /* Configure ENABLE pin for NandFlash */
89 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
91 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
92 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
93 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
94 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
99 vidinfo_t panel_info = {
108 .vl_right_margin = 43,
110 .vl_upper_margin = 4,
111 .vl_lower_margin = 12,
112 .mmio = ATMEL_BASE_LCDC,
115 void lcd_enable(void)
117 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
120 void lcd_disable(void)
122 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
125 #ifdef CONFIG_LCD_INFO
126 void lcd_show_board_info(void)
128 ulong dram_size, nand_size;
132 lcd_printf("%s\n", U_BOOT_VERSION);
133 lcd_printf("ATMEL Corp\n");
134 lcd_printf("at91@atmel.com\n");
135 lcd_printf("%s CPU at %s MHz\n",
137 strmhz(temp, get_cpu_clk_rate()));
140 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
141 dram_size += gd->bd->bi_dram[i].size;
143 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
144 nand_size += nand_info[i].size;
145 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
149 #endif /* CONFIG_LCD_INFO */
150 #endif /* CONFIG_LCD */
152 /* SPI chip select control */
153 #ifdef CONFIG_ATMEL_SPI
155 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
157 return bus == 0 && cs < 2;
160 void spi_cs_activate(struct spi_slave *slave)
164 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
167 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
172 void spi_cs_deactivate(struct spi_slave *slave)
176 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
179 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
183 #endif /* CONFIG_ATMEL_SPI */
185 #ifdef CONFIG_GENERIC_ATMEL_MCI
186 int board_mmc_init(bd_t *bd)
190 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
194 #ifdef CONFIG_KS8851_MLL
195 void at91sam9n12ek_ks8851_hw_init(void)
197 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
199 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
200 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
202 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
203 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
205 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
207 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
208 AT91_SMC_MODE_EXNW_DISABLE |
209 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
210 AT91_SMC_MODE_TDF_CYCLE(1),
213 /* Configure NCS2 PIN */
214 at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
218 int board_early_init_f(void)
220 /* Enable clocks for all PIOs */
221 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
222 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
224 at91_seriald_hw_init();
230 /* adress of boot parameters */
231 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
233 #ifdef CONFIG_NAND_ATMEL
234 at91sam9n12ek_nand_hw_init();
237 #ifdef CONFIG_ATMEL_SPI
238 at91_spi0_hw_init(1 << 0);
245 #ifdef CONFIG_KS8851_MLL
246 at91sam9n12ek_ks8851_hw_init();
252 #ifdef CONFIG_KS8851_MLL
253 int board_eth_init(bd_t *bis)
255 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
261 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
262 CONFIG_SYS_SDRAM_SIZE);