2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/at91sam9rl.h>
28 #include <asm/arch/at91sam9rl_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/gpio.h>
37 #include <atmel_lcdc.h>
38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
42 DECLARE_GLOBAL_DATA_PTR;
44 /* ------------------------------------------------------------------------- */
46 * Miscelaneous platform dependent initialisations
49 #ifdef CONFIG_CMD_NAND
50 static void at91sam9rlek_nand_hw_init(void)
52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
58 csa = readl(&matrix->ebicsa);
59 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
61 writel(csa, &matrix->ebicsa);
63 /* Configure SMC CS3 for NAND/SmartMedia */
64 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
65 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
67 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
68 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
70 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
72 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
73 AT91_SMC_MODE_EXNW_DISABLE |
74 #ifdef CONFIG_SYS_NAND_DBW_16
75 AT91_SMC_MODE_DBW_16 |
76 #else /* CONFIG_SYS_NAND_DBW_8 */
79 AT91_SMC_MODE_TDF_CYCLE(2),
82 writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
84 /* Configure RDY/BSY */
85 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
87 /* Enable NandFlash */
88 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
90 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
91 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
96 vidinfo_t panel_info = {
100 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
101 ATMEL_LCDC_INVFRAME_INVERTED,
110 mmio: ATMEL_BASE_LCDC,
113 void lcd_enable(void)
115 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
118 void lcd_disable(void)
120 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
122 static void at91sam9rlek_lcd_hw_init(void)
124 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
126 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
127 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
128 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
129 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
130 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
131 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
132 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
133 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
134 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
135 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
136 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
137 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
138 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
139 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
140 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
141 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
142 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
143 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
144 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
145 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
146 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
148 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
151 #ifdef CONFIG_LCD_INFO
155 void lcd_show_board_info(void)
157 ulong dram_size, nand_size;
161 lcd_printf ("%s\n", U_BOOT_VERSION);
162 lcd_printf ("(C) 2008 ATMEL Corp\n");
163 lcd_printf ("at91support@atmel.com\n");
164 lcd_printf ("%s CPU at %s MHz\n",
166 strmhz(temp, get_cpu_clk_rate()));
169 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
170 dram_size += gd->bd->bi_dram[i].size;
172 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
173 nand_size += nand_info[i].size;
174 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
178 #endif /* CONFIG_LCD_INFO */
181 int board_early_init_f(void)
183 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
185 /* Enable clocks for all PIOs */
186 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
187 (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
195 /* arch number of AT91SAM9RLEK-Board */
196 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
197 /* adress of boot parameters */
198 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
200 at91_seriald_hw_init();
201 #ifdef CONFIG_CMD_NAND
202 at91sam9rlek_nand_hw_init();
204 #ifdef CONFIG_HAS_DATAFLASH
205 at91_spi0_hw_init(1 << 0);
208 at91sam9rlek_lcd_hw_init();
215 gd->ram_size = get_ram_size(
216 (void *)CONFIG_SYS_SDRAM_BASE,
217 CONFIG_SYS_SDRAM_SIZE);