2 * Copyright (C) 2014 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sama5d3_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/gpio.h>
14 #include <asm/arch/clk.h>
16 #include <asm/arch/atmel_mpddrc.h>
17 #include <asm/arch/at91_wdt.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #ifdef CONFIG_NAND_ATMEL
22 void sama5d3_xplained_nand_hw_init(void)
24 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
26 at91_periph_clk_enable(ATMEL_ID_SMC);
28 /* Configure SMC CS3 for NAND/SmartMedia */
29 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
30 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
32 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
33 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
35 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
37 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
38 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
39 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
40 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
41 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
42 AT91_SMC_MODE_EXNW_DISABLE |
43 #ifdef CONFIG_SYS_NAND_DBW_16
44 AT91_SMC_MODE_DBW_16 |
45 #else /* CONFIG_SYS_NAND_DBW_8 */
48 AT91_SMC_MODE_TDF_CYCLE(3),
54 static void sama5d3_xplained_usb_hw_init(void)
56 at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
57 at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
61 #ifdef CONFIG_GENERIC_ATMEL_MCI
62 static void sama5d3_xplained_mci0_hw_init(void)
64 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
68 int board_early_init_f(void)
70 at91_seriald_hw_init();
77 /* adress of boot parameters */
78 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
80 #ifdef CONFIG_NAND_ATMEL
81 sama5d3_xplained_nand_hw_init();
84 sama5d3_xplained_usb_hw_init();
86 #ifdef CONFIG_GENERIC_ATMEL_MCI
87 sama5d3_xplained_mci0_hw_init();
94 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
95 CONFIG_SYS_SDRAM_SIZE);
101 #ifdef CONFIG_SPL_BUILD
102 void spl_board_init(void)
104 #ifdef CONFIG_SYS_USE_MMC
105 #ifdef CONFIG_GENERIC_ATMEL_MCI
106 sama5d3_xplained_mci0_hw_init();
108 #elif CONFIG_SYS_USE_NANDFLASH
109 sama5d3_xplained_nand_hw_init();
113 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
115 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
117 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
118 ATMEL_MPDDRC_CR_NR_ROW_14 |
119 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
120 ATMEL_MPDDRC_CR_ENRDM_ON |
121 ATMEL_MPDDRC_CR_NB_8BANKS |
122 ATMEL_MPDDRC_CR_NDQS_DISABLED |
123 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
124 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
126 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
127 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
131 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
132 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
133 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
134 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
135 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
136 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
137 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
138 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
140 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
141 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
142 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
143 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
145 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
146 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
147 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
148 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
149 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
154 struct atmel_mpddrc_config ddr2;
158 /* Enable MPDDR clock */
159 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
160 at91_system_clk_enable(AT91_PMC_DDR);
162 /* DDRAM2 Controller initialize */
163 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
166 void at91_pmc_init(void)
170 tmp = AT91_PMC_PLLAR_29 |
171 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
172 AT91_PMC_PLLXR_MUL(43) |
173 AT91_PMC_PLLXR_DIV(1);
176 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
178 tmp = AT91_PMC_MCKR_MDIV_4 |
179 AT91_PMC_MCKR_CSS_PLLA;