2 * Copyright (C) 2014 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <atmel_mci.h>
20 #include <asm/arch/atmel_mpddrc.h>
21 #include <asm/arch/at91_wdt.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_NAND_ATMEL
26 void sama5d3_xplained_nand_hw_init(void)
28 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
30 at91_periph_clk_enable(ATMEL_ID_SMC);
32 /* Configure SMC CS3 for NAND/SmartMedia */
33 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
34 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
36 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
37 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
39 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
41 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
42 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
43 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
44 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
45 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
46 AT91_SMC_MODE_EXNW_DISABLE |
47 #ifdef CONFIG_SYS_NAND_DBW_16
48 AT91_SMC_MODE_DBW_16 |
49 #else /* CONFIG_SYS_NAND_DBW_8 */
52 AT91_SMC_MODE_TDF_CYCLE(3),
58 static void sama5d3_xplained_usb_hw_init(void)
60 at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
61 at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
65 #ifdef CONFIG_GENERIC_ATMEL_MCI
66 static void sama5d3_xplained_mci0_hw_init(void)
70 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
74 int board_early_init_f(void)
76 at91_periph_clk_enable(ATMEL_ID_PIOA);
77 at91_periph_clk_enable(ATMEL_ID_PIOB);
78 at91_periph_clk_enable(ATMEL_ID_PIOC);
79 at91_periph_clk_enable(ATMEL_ID_PIOD);
80 at91_periph_clk_enable(ATMEL_ID_PIOE);
82 at91_seriald_hw_init();
89 /* adress of boot parameters */
90 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
92 #ifdef CONFIG_NAND_ATMEL
93 sama5d3_xplained_nand_hw_init();
96 sama5d3_xplained_usb_hw_init();
98 #ifdef CONFIG_GENERIC_ATMEL_MCI
99 sama5d3_xplained_mci0_hw_init();
110 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
111 CONFIG_SYS_SDRAM_SIZE);
116 int board_eth_init(bd_t *bis)
119 macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
120 macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
125 #ifdef CONFIG_GENERIC_ATMEL_MCI
126 int board_mmc_init(bd_t *bis)
128 atmel_mci_init((void *)ATMEL_BASE_MCI0);
135 #ifdef CONFIG_SPL_BUILD
136 void spl_board_init(void)
138 #ifdef CONFIG_SYS_USE_MMC
139 sama5d3_xplained_mci0_hw_init();
140 #elif CONFIG_SYS_USE_NANDFLASH
141 sama5d3_xplained_nand_hw_init();
145 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
147 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
149 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
150 ATMEL_MPDDRC_CR_NR_ROW_14 |
151 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
152 ATMEL_MPDDRC_CR_ENRDM_ON |
153 ATMEL_MPDDRC_CR_NB_8BANKS |
154 ATMEL_MPDDRC_CR_NDQS_DISABLED |
155 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
156 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
158 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
159 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
163 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
164 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
166 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
168 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
169 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
170 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
172 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
173 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
174 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
175 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
177 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
178 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
179 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
180 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
181 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
186 struct atmel_mpddrc_config ddr2;
190 /* Enable MPDDR clock */
191 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
192 at91_system_clk_enable(AT91_PMC_DDR);
194 /* DDRAM2 Controller initialize */
195 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
198 void at91_pmc_init(void)
202 tmp = AT91_PMC_PLLAR_29 |
203 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
204 AT91_PMC_PLLXR_MUL(43) |
205 AT91_PMC_PLLXR_DIV(1);
208 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
210 tmp = AT91_PMC_MCKR_MDIV_4 |
211 AT91_PMC_MCKR_CSS_PLLA;