2 * Copyright (C) 2014 Atmel
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_pmc.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/atmel_mpddrc.h>
14 #include <asm/arch/atmel_usba_udc.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/sama5d3_smc.h>
18 #include <asm/arch/sama5d4.h>
19 #include <atmel_hlcdc.h>
20 #include <atmel_mci.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #ifdef CONFIG_ATMEL_SPI
31 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
33 return bus == 0 && cs == 0;
36 void spi_cs_activate(struct spi_slave *slave)
38 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
41 void spi_cs_deactivate(struct spi_slave *slave)
43 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
46 static void sama5d4_xplained_spi0_hw_init(void)
48 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
49 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
50 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
52 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
55 at91_periph_clk_enable(ATMEL_ID_SPI0);
57 #endif /* CONFIG_ATMEL_SPI */
59 #ifdef CONFIG_NAND_ATMEL
60 static void sama5d4_xplained_nand_hw_init(void)
62 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
64 at91_periph_clk_enable(ATMEL_ID_SMC);
66 /* Configure SMC CS3 for NAND */
67 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
68 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
70 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
73 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
75 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
76 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
77 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
78 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
79 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
80 AT91_SMC_MODE_EXNW_DISABLE |
82 AT91_SMC_MODE_TDF_CYCLE(3),
85 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
86 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
87 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
88 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
89 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
90 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
91 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
92 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
93 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
94 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
95 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
96 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
97 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
98 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
102 #ifdef CONFIG_CMD_USB
103 static void sama5d4_xplained_usb_hw_init(void)
105 at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
106 at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
111 vidinfo_t panel_info = {
119 .vl_right_margin = 2,
121 .vl_upper_margin = 2,
122 .vl_lower_margin = 2,
123 .mmio = ATMEL_BASE_LCDC,
126 /* No power up/down pin for the LCD pannel */
127 void lcd_enable(void) { /* Empty! */ }
128 void lcd_disable(void) { /* Empty! */ }
130 unsigned int has_lcdc(void)
135 static void sama5d4_xplained_lcd_hw_init(void)
137 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
138 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
139 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
140 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
141 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
142 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
144 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
145 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
146 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
147 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
148 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
149 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
150 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
151 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
153 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
154 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
155 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
156 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
157 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
158 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
159 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
160 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
162 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
163 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
164 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
165 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
166 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
167 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
168 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
169 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
172 at91_periph_clk_enable(ATMEL_ID_LCDC);
175 #ifdef CONFIG_LCD_INFO
176 void lcd_show_board_info(void)
178 ulong dram_size, nand_size;
182 lcd_printf("2014 ATMEL Corp\n");
183 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
184 strmhz(temp, get_cpu_clk_rate()));
187 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
188 dram_size += gd->bd->bi_dram[i].size;
191 #ifdef CONFIG_NAND_ATMEL
192 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
193 nand_size += nand_info[i].size;
195 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
196 dram_size >> 20, nand_size >> 20);
198 #endif /* CONFIG_LCD_INFO */
200 #endif /* CONFIG_LCD */
202 #ifdef CONFIG_GENERIC_ATMEL_MCI
203 void sama5d4_xplained_mci1_hw_init(void)
205 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
206 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
207 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
208 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
209 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
210 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
213 * As the mci io internal pull down is too strong, so if the io needs
214 * external pull up, the pull up resistor will be very small, if so
215 * the power consumption will increase, so disable the interanl pull
216 * down to save the power.
218 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
219 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
220 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
221 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
222 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
223 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
226 at91_periph_clk_enable(ATMEL_ID_MCI1);
229 int board_mmc_init(bd_t *bis)
231 return atmel_mci_init((void *)ATMEL_BASE_MCI1);
233 #endif /* CONFIG_GENERIC_ATMEL_MCI */
236 void sama5d4_xplained_macb0_hw_init(void)
238 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
239 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
240 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
241 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
242 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
243 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
244 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
245 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
246 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
247 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
250 at91_periph_clk_enable(ATMEL_ID_GMAC0);
254 static void sama5d4_xplained_serial3_hw_init(void)
256 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
257 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
260 at91_periph_clk_enable(ATMEL_ID_USART3);
263 int board_early_init_f(void)
265 at91_periph_clk_enable(ATMEL_ID_PIOA);
266 at91_periph_clk_enable(ATMEL_ID_PIOB);
267 at91_periph_clk_enable(ATMEL_ID_PIOC);
268 at91_periph_clk_enable(ATMEL_ID_PIOD);
269 at91_periph_clk_enable(ATMEL_ID_PIOE);
271 sama5d4_xplained_serial3_hw_init();
278 /* adress of boot parameters */
279 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
281 #ifdef CONFIG_ATMEL_SPI
282 sama5d4_xplained_spi0_hw_init();
284 #ifdef CONFIG_NAND_ATMEL
285 sama5d4_xplained_nand_hw_init();
287 #ifdef CONFIG_GENERIC_ATMEL_MCI
288 sama5d4_xplained_mci1_hw_init();
291 sama5d4_xplained_macb0_hw_init();
294 sama5d4_xplained_lcd_hw_init();
296 #ifdef CONFIG_CMD_USB
297 sama5d4_xplained_usb_hw_init();
299 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
308 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
309 CONFIG_SYS_SDRAM_SIZE);
313 int board_eth_init(bd_t *bis)
318 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
321 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
322 usba_udc_probe(&pdata);
323 #ifdef CONFIG_USB_ETH_RNDIS
324 usb_eth_initialize(bis);
332 #ifdef CONFIG_SPL_BUILD
333 void spl_board_init(void)
335 #ifdef CONFIG_SYS_USE_MMC
336 sama5d4_xplained_mci1_hw_init();
337 #elif CONFIG_SYS_USE_NANDFLASH
338 sama5d4_xplained_nand_hw_init();
339 #elif CONFIG_SYS_USE_SERIALFLASH
340 sama5d4_xplained_spi0_hw_init();
344 static void ddr2_conf(struct atmel_mpddr *ddr2)
346 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
348 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
349 ATMEL_MPDDRC_CR_NR_ROW_14 |
350 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
351 ATMEL_MPDDRC_CR_NB_8BANKS |
352 ATMEL_MPDDRC_CR_NDQS_DISABLED |
353 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
354 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
358 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
359 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
360 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
361 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
362 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
363 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
364 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
365 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
367 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
368 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
369 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
370 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
372 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
373 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
374 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
375 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
376 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
381 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
382 struct atmel_mpddr ddr2;
386 /* enable MPDDR clock */
387 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
388 writel(0x4, &pmc->scer);
390 /* DDRAM2 Controller initialize */
391 ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
394 void at91_pmc_init(void)
396 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
399 tmp = AT91_PMC_PLLAR_29 |
400 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
401 AT91_PMC_PLLXR_MUL(87) |
402 AT91_PMC_PLLXR_DIV(1);
405 writel(0x0 << 8, &pmc->pllicpr);
407 tmp = AT91_PMC_MCKR_H32MXDIV |
408 AT91_PMC_MCKR_PLLADIV_2 |
409 AT91_PMC_MCKR_MDIV_3 |
410 AT91_PMC_MCKR_CSS_PLLA;