2 * Copyright (C) 2014 Atmel
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_pmc.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/gpio.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/sama5d3_smc.h>
16 #include <asm/arch/sama5d4.h>
17 #include <atmel_hlcdc.h>
18 #include <atmel_mci.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_ATMEL_SPI
29 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
31 return bus == 0 && cs == 0;
34 void spi_cs_activate(struct spi_slave *slave)
36 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
39 void spi_cs_deactivate(struct spi_slave *slave)
41 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
44 static void sama5d4ek_spi0_hw_init(void)
46 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
47 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
48 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
50 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
53 at91_periph_clk_enable(ATMEL_ID_SPI0);
55 #endif /* CONFIG_ATMEL_SPI */
57 #ifdef CONFIG_NAND_ATMEL
58 static void sama5d4ek_nand_hw_init(void)
60 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
62 at91_periph_clk_enable(ATMEL_ID_SMC);
64 /* Configure SMC CS3 for NAND */
65 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
66 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
68 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
69 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
71 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
73 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
74 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
75 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
76 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
78 AT91_SMC_MODE_EXNW_DISABLE |
80 AT91_SMC_MODE_TDF_CYCLE(3),
83 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
84 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
85 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
86 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
87 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
88 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
89 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
90 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
91 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
92 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
93 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
94 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
95 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
96 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
100 #ifdef CONFIG_CMD_USB
101 static void sama5d4ek_usb_hw_init(void)
103 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
104 at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
105 at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
110 vidinfo_t panel_info = {
117 .vl_left_margin = 128,
118 .vl_right_margin = 0,
120 .vl_upper_margin = 23,
121 .vl_lower_margin = 22,
122 .mmio = ATMEL_BASE_LCDC,
125 /* No power up/down pin for the LCD pannel */
126 void lcd_enable(void) { /* Empty! */ }
127 void lcd_disable(void) { /* Empty! */ }
129 unsigned int has_lcdc(void)
134 static void sama5d4ek_lcd_hw_init(void)
136 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
137 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
138 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
139 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
140 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
141 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
143 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
144 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
145 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
146 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
147 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
148 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
150 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
151 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
152 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
153 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
154 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
155 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
157 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
158 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
159 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
160 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
161 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
162 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
165 at91_periph_clk_enable(ATMEL_ID_LCDC);
168 #ifdef CONFIG_LCD_INFO
169 void lcd_show_board_info(void)
171 ulong dram_size, nand_size;
175 lcd_printf("2014 ATMEL Corp\n");
176 lcd_printf("at91@atmel.com\n");
177 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
178 strmhz(temp, get_cpu_clk_rate()));
181 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
182 dram_size += gd->bd->bi_dram[i].size;
185 #ifdef CONFIG_NAND_ATMEL
186 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
187 nand_size += nand_info[i].size;
189 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
190 dram_size >> 20, nand_size >> 20);
192 #endif /* CONFIG_LCD_INFO */
194 #endif /* CONFIG_LCD */
196 #ifdef CONFIG_GENERIC_ATMEL_MCI
197 void sama5d4ek_mci1_hw_init(void)
199 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
200 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
201 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
202 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
203 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
204 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
207 * As the mci io internal pull down is too strong, so if the io needs
208 * external pull up, the pull up resistor will be very small, if so
209 * the power consumption will increase, so disable the interanl pull
210 * down to save the power.
212 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
213 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
214 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
215 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
216 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
217 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
220 at91_periph_clk_enable(ATMEL_ID_MCI1);
223 int board_mmc_init(bd_t *bis)
225 /* Enable power for MCI1 interface */
226 at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
228 return atmel_mci_init((void *)ATMEL_BASE_MCI1);
230 #endif /* CONFIG_GENERIC_ATMEL_MCI */
233 void sama5d4ek_macb0_hw_init(void)
235 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
236 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
237 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
238 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
239 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
240 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
241 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
242 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
243 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
244 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
247 at91_periph_clk_enable(ATMEL_ID_GMAC0);
251 static void sama5d4ek_serial3_hw_init(void)
253 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
254 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
257 at91_periph_clk_enable(ATMEL_ID_USART3);
260 int board_early_init_f(void)
262 at91_periph_clk_enable(ATMEL_ID_PIOA);
263 at91_periph_clk_enable(ATMEL_ID_PIOB);
264 at91_periph_clk_enable(ATMEL_ID_PIOC);
265 at91_periph_clk_enable(ATMEL_ID_PIOD);
266 at91_periph_clk_enable(ATMEL_ID_PIOE);
268 sama5d4ek_serial3_hw_init();
275 /* adress of boot parameters */
276 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
278 #ifdef CONFIG_ATMEL_SPI
279 sama5d4ek_spi0_hw_init();
281 #ifdef CONFIG_NAND_ATMEL
282 sama5d4ek_nand_hw_init();
284 #ifdef CONFIG_GENERIC_ATMEL_MCI
285 sama5d4ek_mci1_hw_init();
288 sama5d4ek_macb0_hw_init();
291 sama5d4ek_lcd_hw_init();
293 #ifdef CONFIG_CMD_USB
294 sama5d4ek_usb_hw_init();
302 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
303 CONFIG_SYS_SDRAM_SIZE);
307 int board_eth_init(bd_t *bis)
312 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);