3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_pci.h>
32 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #include <fdt_support.h>
40 long int fixed_sdram(void);
42 int board_early_init_f (void)
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
51 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
53 if ((uint)&gur->porpllsr != 0xe00e0000) {
54 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
56 printf ("Board: ATUM8548\n");
58 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
59 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
60 ecm->eedr = 0xffffffff; /* Clear ecm errors */
61 ecm->eeer = 0xffffffff; /* Enable ecm errors */
66 #if !defined(CONFIG_SPD_EEPROM)
67 /*************************************************************************
68 * fixed sdram init -- doesn't use serial presence detect.
69 ************************************************************************/
70 long int fixed_sdram (void)
72 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
74 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
75 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
81 #if defined (CONFIG_DDR_ECC)
82 ddr->err_disable = 0x0000000D;
83 ddr->err_sbe = 0x00ff0000;
85 asm("sync;isync;msync");
87 #if defined (CONFIG_DDR_ECC)
88 /* Enable ECC checking */
89 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
91 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
93 asm("sync; isync; msync");
95 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
97 #endif /* !defined(CONFIG_SPD_EEPROM) */
100 initdram(int board_type)
104 puts("Initializing\n");
106 #if defined(CONFIG_SPD_EEPROM)
107 puts("fsl_ddr_sdram\n");
108 dram_size = fsl_ddr_sdram();
109 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
110 dram_size *= 0x100000;
112 puts("fixed_sdram\n");
113 dram_size = fixed_sdram ();
120 #if defined(CONFIG_SYS_DRAM_TEST)
124 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
125 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
128 printf("Testing DRAM from 0x%08x to 0x%08x\n",
129 CONFIG_SYS_MEMTEST_START,
130 CONFIG_SYS_MEMTEST_END);
132 printf("DRAM test phase 1:\n");
133 for (p = pstart; p < pend; p++) {
134 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
138 for (p = pstart; p < pend; p++) {
139 if (*p != 0xaaaaaaaa) {
140 printf ("DRAM test fails at: %08x\n", (uint) p);
145 printf("DRAM test phase 2:\n");
146 for (p = pstart; p < pend; p++)
149 for (p = pstart; p < pend; p++) {
150 if (*p != 0x55555555) {
151 printf ("DRAM test fails at: %08x\n", (uint) p);
156 printf("DRAM test passed.\n");
162 static struct pci_controller pci1_hose;
166 static struct pci_controller pci2_hose;
170 static struct pci_controller pcie1_hose;
173 void pci_init_board(void)
175 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
176 struct fsl_pci_info pci_info[3];
177 u32 devdisr, pordevsr, io_sel;
178 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
179 int first_free_busno = 0;
182 int pcie_ep, pcie_configured;
184 devdisr = in_be32(&gur->devdisr);
185 pordevsr = in_be32(&gur->pordevsr);
186 porpllsr = in_be32(&gur->porpllsr);
187 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
189 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
191 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
192 setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR);
195 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
196 printf (" eTSEC1 is in sgmii mode.\n");
197 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
198 printf (" eTSEC2 is in sgmii mode.\n");
199 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
200 printf (" eTSEC3 is in sgmii mode.\n");
201 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
202 printf (" eTSEC4 is in sgmii mode.\n");
206 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
208 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
209 SET_STD_PCIE_INFO(pci_info[num], 1);
210 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
211 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
212 /* outbound memory */
213 pci_set_region(&pcie1_hose.regions[0],
214 CONFIG_SYS_PCIE1_MEM_BUS2,
215 CONFIG_SYS_PCIE1_MEM_PHYS2,
216 CONFIG_SYS_PCIE1_MEM_SIZE2,
219 pcie1_hose.region_count = 1;
221 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
222 pcie_ep ? "End Point" : "Root Complex",
225 first_free_busno = fsl_pci_init_port(&pci_info[num++],
226 &pcie1_hose, first_free_busno);
228 printf (" PCIE1: disabled\n");
233 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
237 pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
238 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
239 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
240 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
242 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
243 SET_STD_PCI_INFO(pci_info[num], 1);
244 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
245 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
247 (pci_speed == 33333000) ? "33" :
248 (pci_speed == 66666000) ? "66" : "unknown",
249 pci_clk_sel ? "sync" : "async",
250 pci_agent ? "agent" : "host",
251 pci_arb ? "arbiter" : "external-arbiter",
254 first_free_busno = fsl_pci_init_port(&pci_info[num++],
255 &pci1_hose, first_free_busno);
257 printf (" PCI: disabled\n");
262 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
266 if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
267 SET_STD_PCI_INFO(pci_info[num], 2);
268 pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 &pci1_hose, first_free_busno);
274 printf (" PCI2: disabled\n");
278 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
283 int last_stage_init(void)
285 int ic = icache_status ();
286 printf ("icache_status: %d\n", ic);
290 #if defined(CONFIG_OF_BOARD_SETUP)
291 void ft_board_setup(void *blob, bd_t *bd)
293 ft_cpu_setup(blob, bd);
296 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
299 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
302 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);