3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_pci.h>
32 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #include <fdt_support.h>
40 long int fixed_sdram(void);
42 int board_early_init_f (void)
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
51 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
53 if ((uint)&gur->porpllsr != 0xe00e0000) {
54 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
56 printf ("Board: ATUM8548\n");
58 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
59 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
60 ecm->eedr = 0xffffffff; /* Clear ecm errors */
61 ecm->eeer = 0xffffffff; /* Enable ecm errors */
66 #if !defined(CONFIG_SPD_EEPROM)
67 /*************************************************************************
68 * fixed sdram init -- doesn't use serial presence detect.
69 ************************************************************************/
70 long int fixed_sdram (void)
72 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
74 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
75 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
81 #if defined (CONFIG_DDR_ECC)
82 ddr->err_disable = 0x0000000D;
83 ddr->err_sbe = 0x00ff0000;
85 asm("sync;isync;msync");
87 #if defined (CONFIG_DDR_ECC)
88 /* Enable ECC checking */
89 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
91 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
93 asm("sync; isync; msync");
95 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
97 #endif /* !defined(CONFIG_SPD_EEPROM) */
100 initdram(int board_type)
104 puts("Initializing\n");
106 #if defined(CONFIG_SPD_EEPROM)
107 puts("fsl_ddr_sdram\n");
108 dram_size = fsl_ddr_sdram();
109 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
110 dram_size *= 0x100000;
112 puts("fixed_sdram\n");
113 dram_size = fixed_sdram ();
120 #if defined(CONFIG_SYS_DRAM_TEST)
124 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
125 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
128 printf("Testing DRAM from 0x%08x to 0x%08x\n",
129 CONFIG_SYS_MEMTEST_START,
130 CONFIG_SYS_MEMTEST_END);
132 printf("DRAM test phase 1:\n");
133 for (p = pstart; p < pend; p++) {
134 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
138 for (p = pstart; p < pend; p++) {
139 if (*p != 0xaaaaaaaa) {
140 printf ("DRAM test fails at: %08x\n", (uint) p);
145 printf("DRAM test phase 2:\n");
146 for (p = pstart; p < pend; p++)
149 for (p = pstart; p < pend; p++) {
150 if (*p != 0x55555555) {
151 printf ("DRAM test fails at: %08x\n", (uint) p);
156 printf("DRAM test passed.\n");
162 static struct pci_controller pci1_hose;
166 static struct pci_controller pci2_hose;
170 static struct pci_controller pcie1_hose;
173 int first_free_busno=0;
175 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
176 extern void fsl_pci_init(struct pci_controller *hose);
181 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
183 uint devdisr = gur->devdisr;
184 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
185 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
187 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
188 devdisr, io_sel, host_agent);
190 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
191 gur->clkocr |= MPC85xx_ATUM_CLKOCR;
194 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
195 printf (" eTSEC1 is in sgmii mode.\n");
196 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
197 printf (" eTSEC2 is in sgmii mode.\n");
198 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
199 printf (" eTSEC3 is in sgmii mode.\n");
200 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
201 printf (" eTSEC4 is in sgmii mode.\n");
206 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
207 struct pci_controller *hose = &pcie1_hose;
208 int pcie_ep = (host_agent == 5);
209 int pcie_configured = io_sel & 6;
210 struct pci_region *r = hose->regions;
212 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
213 printf ("\n PCIE1 connected to slot as %s (base address %x)",
214 pcie_ep ? "End Point" : "Root Complex",
216 if (pci->pme_msg_det) {
217 pci->pme_msg_det = 0xffffffff;
218 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
223 r += fsl_pci_setup_inbound_windows(r);
225 /* outbound memory */
227 CONFIG_SYS_PCIE1_MEM_BASE,
228 CONFIG_SYS_PCIE1_MEM_PHYS,
229 CONFIG_SYS_PCIE1_MEM_SIZE,
234 CONFIG_SYS_PCIE1_IO_BASE,
235 CONFIG_SYS_PCIE1_IO_PHYS,
236 CONFIG_SYS_PCIE1_IO_SIZE,
239 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
240 /* outbound memory */
242 CONFIG_SYS_PCIE1_MEM_BASE2,
243 CONFIG_SYS_PCIE1_MEM_PHYS2,
244 CONFIG_SYS_PCIE1_MEM_SIZE2,
247 hose->region_count = r - hose->regions;
248 hose->first_busno=first_free_busno;
250 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
254 first_free_busno=hose->last_busno+1;
255 printf(" PCIE1 on bus %02x - %02x\n",
256 hose->first_busno,hose->last_busno);
259 printf (" PCIE1: disabled\n");
264 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
269 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
270 struct pci_controller *hose = &pci1_hose;
271 struct pci_region *r = hose->regions;
273 uint pci_agent = (host_agent == 6);
274 uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
275 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
276 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
277 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
279 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
280 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
282 (pci_speed == 33333000) ? "33" :
283 (pci_speed == 66666000) ? "66" : "unknown",
284 pci_clk_sel ? "sync" : "async",
285 pci_agent ? "agent" : "host",
286 pci_arb ? "arbiter" : "external-arbiter",
291 r += fsl_pci_setup_inbound_windows(r);
293 /* outbound memory */
295 CONFIG_SYS_PCI1_MEM_BASE,
296 CONFIG_SYS_PCI1_MEM_PHYS,
297 CONFIG_SYS_PCI1_MEM_SIZE,
302 CONFIG_SYS_PCI1_IO_BASE,
303 CONFIG_SYS_PCI1_IO_PHYS,
304 CONFIG_SYS_PCI1_IO_SIZE,
306 hose->region_count = r - hose->regions;
307 hose->first_busno=first_free_busno;
308 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
311 first_free_busno=hose->last_busno+1;
312 printf ("PCI1 on bus %02x - %02x\n",
313 hose->first_busno,hose->last_busno);
315 printf (" PCI1: disabled\n");
319 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
324 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
325 extern void fsl_pci_init(struct pci_controller *hose);
326 struct pci_controller *hose = &pci2_hose;
327 struct pci_region *r = hose->regions;
329 if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
330 r += fsl_pci_setup_inbound_windows(r);
333 CONFIG_SYS_PCI2_MEM_BASE,
334 CONFIG_SYS_PCI2_MEM_PHYS,
335 CONFIG_SYS_PCI2_MEM_SIZE,
339 CONFIG_SYS_PCI2_IO_BASE,
340 CONFIG_SYS_PCI2_IO_PHYS,
341 CONFIG_SYS_PCI2_IO_SIZE,
343 hose->region_count = r - hose->regions;
344 hose->first_busno=first_free_busno;
345 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
348 first_free_busno=hose->last_busno+1;
349 printf ("PCI2 on bus %02x - %02x\n",
350 hose->first_busno,hose->last_busno);
352 printf (" PCI2: disabled\n");
356 gur->devdisr |= MPC85xx_DEVDISR_PCI2;
361 int last_stage_init(void)
363 int ic = icache_status ();
364 printf ("icache_status: %d\n", ic);
368 #if defined(CONFIG_OF_BOARD_SETUP)
369 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
370 struct pci_controller *hose);
372 void ft_board_setup(void *blob, bd_t *bd)
374 ft_cpu_setup(blob, bd);
377 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
380 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
383 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);