1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014, Bachmann electronic GmbH
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/sata.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/sys_proto.h>
21 #include <fsl_esdhc.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
36 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
42 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
45 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
46 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50 gd->ram_size = imx_ddr_size();
55 static iomux_v3_cfg_t const uart1_pads[] = {
56 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
57 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 static void setup_iomux_uart(void)
62 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
65 static iomux_v3_cfg_t const enet_pads[] = {
66 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 static void setup_iomux_enet(void)
87 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
90 static iomux_v3_cfg_t const ecspi1_pads[] = {
91 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
92 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
93 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
94 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
95 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
98 static void setup_iomux_spi(void)
100 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
103 int board_spi_cs_gpio(unsigned bus, unsigned cs)
105 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
108 static iomux_v3_cfg_t const feature_pads[] = {
110 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
113 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
116 static void setup_iomux_features(void)
118 imx_iomux_v3_setup_multiple_pads(feature_pads,
119 ARRAY_SIZE(feature_pads));
122 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
125 static struct i2c_pads_info i2c_pad_info1 = {
127 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
128 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
129 .gp = IMX_GPIO_NR(2, 30)
132 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
133 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
134 .gp = IMX_GPIO_NR(3, 16)
138 /* I2C3 - IO expander */
139 static struct i2c_pads_info i2c_pad_info2 = {
141 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
142 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
143 .gp = IMX_GPIO_NR(3, 17)
146 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
147 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
148 .gp = IMX_GPIO_NR(3, 18)
152 static void setup_iomux_i2c(void)
154 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
155 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
158 static void ccgr_init(void)
160 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
162 writel(0x00C03F3F, &ccm->CCGR0);
163 writel(0x0030FC33, &ccm->CCGR1);
164 writel(0x0FFFC000, &ccm->CCGR2);
165 writel(0x3FF00000, &ccm->CCGR3);
166 writel(0x00FFF300, &ccm->CCGR4);
167 writel(0x0F0000C3, &ccm->CCGR5);
168 writel(0x000003FF, &ccm->CCGR6);
171 int board_early_init_f(void)
179 setup_iomux_features();
184 static iomux_v3_cfg_t const usdhc3_pads[] = {
185 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
190 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
192 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
194 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 iomux_v3_cfg_t const usdhc4_pads[] = {
199 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
201 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
202 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
203 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
204 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
207 int board_mmc_getcd(struct mmc *mmc)
209 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
212 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
213 gpio_direction_input(IMX_GPIO_NR(4, 5));
214 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
216 gpio_direction_input(IMX_GPIO_NR(1, 5));
217 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
223 struct fsl_esdhc_cfg usdhc_cfg[2] = {
228 int board_mmc_init(bd_t *bis)
233 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
234 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
236 usdhc_cfg[0].max_bus_width = 8;
237 usdhc_cfg[1].max_bus_width = 4;
239 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
242 imx_iomux_v3_setup_multiple_pads(
243 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
246 imx_iomux_v3_setup_multiple_pads(
247 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
250 printf("Warning: you configured more USDHC controllers"
251 "(%d) then supported by the board (%d)\n",
252 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
256 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
264 static void leds_on(void)
266 /* turn on all possible leds connected via GPIO expander */
268 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
269 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
272 static void backlight_lcd_off(void)
274 unsigned gpio = IMX_GPIO_NR(2, 0);
275 gpio_direction_output(gpio, 0);
277 gpio = IMX_GPIO_NR(2, 3);
278 gpio_direction_output(gpio, 0);
281 int board_eth_init(bd_t *bis)
283 uint32_t base = IMX_FEC_BASE;
284 struct mii_dev *bus = NULL;
285 struct phy_device *phydev = NULL;
290 bus = fec_get_miibus(base, -1);
294 /* scan phy 0 and 5 */
295 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
301 /* depending on the phy address we can detect our board version */
302 if (phydev->addr == 0)
303 env_set("boardver", "");
305 env_set("boardver", "mr");
307 printf("using phy at %d\n", phydev->addr);
308 ret = fec_probe(bis, -1, base, bus, phydev);
323 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
338 puts("Board: "CONFIG_SYS_BOARD"\n");
342 #ifdef CONFIG_CMD_BMODE
343 static const struct boot_mode board_boot_modes[] = {
344 /* 4 bit bus width */
345 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
350 int misc_init_r(void)
352 #ifdef CONFIG_CMD_BMODE
353 add_board_boot_modes(board_boot_modes);