4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/hardware.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 void balloon3_init_fpga(void);
34 * Miscelaneous platform dependent initialisations
39 /* We have RAM, disable cache */
43 /* arch number of vpac270 */
44 gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
46 /* adress of boot parameters */
47 gd->bd->bi_boot_params = 0xa0000100;
55 struct serial_device *default_serial_console(void)
57 return &serial_stuart_device;
60 extern void pxa_dram_init(void);
64 gd->ram_size = PHYS_SDRAM_1_SIZE;
68 void dram_init_banksize(void)
70 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
71 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
72 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
74 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
75 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
76 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
80 int usb_board_init(void)
82 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
83 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
86 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
88 while (readl(UHCHR) & UHCHR_FSBIR)
91 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
92 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
94 /* Clear any OTG Pin Hold */
95 if (readl(PSSR) & PSSR_OTGPH)
96 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
98 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
99 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
101 /* Set port power control mask bits, only 3 ports. */
102 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
105 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
106 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
111 void usb_board_init_fail(void)
116 void usb_board_stop(void)
118 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
120 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
122 writel(readl(UHCCOMS) | 1, UHCCOMS);
125 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
131 #if defined(CONFIG_FPGA)
132 /* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
133 int fpga_pgm_fn(int nassert, int nflush, int cookie)
140 writel(0x100, GPCR3);
142 writel(0x100, GPSR3);
146 /* Check GPIO83 -- INITB */
147 int fpga_init_fn(int cookie)
149 return !(readl(GPLR2) & 0x80000);
152 /* Check GPIO84 -- BUSY */
153 int fpga_busy_fn(int cookie)
155 return !(readl(GPLR2) & 0x100000);
158 /* Check GPIO111 -- DONE */
159 int fpga_done_fn(int cookie)
161 return readl(GPLR3) & 0x8000;
164 /* Configure GPIO104 as GPIO and deassert it */
165 int fpga_pre_config_fn(int cookie)
167 writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
168 writel(0x100, GPCR3);
172 /* Configure GPIO104 as nSKTSEL */
173 int fpga_post_config_fn(int cookie)
175 writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
180 int fpga_wr_fn(int nassert_write, int flush, int cookie)
185 writel(0x100, GPCR3);
187 writel(0x100, GPSR3);
189 return nassert_write;
192 /* Write program to the FPGA */
193 int fpga_wdata_fn(uchar data, int flush, int cookie)
195 writeb(data, 0x10f00000);
199 /* Toggle Clock pin -- NO-OP */
200 int fpga_clk_fn(int assert_clk, int flush, int cookie)
205 /* Toggle ChipSelect pin -- NO-OP */
206 int fpga_cs_fn(int assert_clk, int flush, int cookie)
211 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
227 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
228 (void *)&balloon3_fpga_fns, 0);
230 /* Initialize the FPGA */
231 void balloon3_init_fpga(void)
234 fpga_add(fpga_xilinx, &fpga);
237 void balloon3_init_fpga(void) {}
238 #endif /* CONFIG_FPGA */