4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/pxa.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 void balloon3_init_fpga(void);
23 * Miscelaneous platform dependent initialisations
28 /* We have RAM, disable cache */
32 /* arch number of vpac270 */
33 gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
35 /* adress of boot parameters */
36 gd->bd->bi_boot_params = 0xa0000100;
47 gd->ram_size = PHYS_SDRAM_1_SIZE;
51 void dram_init_banksize(void)
53 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
54 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
55 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
57 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
58 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
59 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
63 int board_usb_init(int index, enum usb_init_type init)
65 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
66 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
69 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
71 while (readl(UHCHR) & UHCHR_FSBIR)
74 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
75 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
77 /* Clear any OTG Pin Hold */
78 if (readl(PSSR) & PSSR_OTGPH)
79 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
81 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
82 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
84 /* Set port power control mask bits, only 3 ports. */
85 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
88 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
89 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
94 int board_usb_cleanup(int index, enum usb_init_type init)
99 void usb_board_stop(void)
101 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
103 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
105 writel(readl(UHCCOMS) | 1, UHCCOMS);
108 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
114 #if defined(CONFIG_FPGA)
115 /* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
116 int fpga_pgm_fn(int nassert, int nflush, int cookie)
123 writel(0x100, GPCR3);
125 writel(0x100, GPSR3);
129 /* Check GPIO83 -- INITB */
130 int fpga_init_fn(int cookie)
132 return !(readl(GPLR2) & 0x80000);
135 /* Check GPIO84 -- BUSY */
136 int fpga_busy_fn(int cookie)
138 return !(readl(GPLR2) & 0x100000);
141 /* Check GPIO111 -- DONE */
142 int fpga_done_fn(int cookie)
144 return readl(GPLR3) & 0x8000;
147 /* Configure GPIO104 as GPIO and deassert it */
148 int fpga_pre_config_fn(int cookie)
150 writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
151 writel(0x100, GPCR3);
155 /* Configure GPIO104 as nSKTSEL */
156 int fpga_post_config_fn(int cookie)
158 writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
163 int fpga_wr_fn(int nassert_write, int flush, int cookie)
168 writel(0x100, GPCR3);
170 writel(0x100, GPSR3);
172 return nassert_write;
175 /* Write program to the FPGA */
176 int fpga_wdata_fn(uchar data, int flush, int cookie)
178 writeb(data, 0x10f00000);
182 /* Toggle Clock pin -- NO-OP */
183 int fpga_clk_fn(int assert_clk, int flush, int cookie)
188 /* Toggle ChipSelect pin -- NO-OP */
189 int fpga_cs_fn(int assert_clk, int flush, int cookie)
194 xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
210 xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
211 (void *)&balloon3_fpga_fns, 0);
213 /* Initialize the FPGA */
214 void balloon3_init_fpga(void)
217 fpga_add(fpga_xilinx, &fpga);
220 void balloon3_init_fpga(void) {}
221 #endif /* CONFIG_FPGA */