3 * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 * Jason Liu <r64343@freescale.com>
8 * SPDX-License-Identifier: GPL-2.0+
10 * Refer docs/README.imxmage for more details about how-to configure
11 * and create imximage boot image
13 * The syntax is taken as close as possible with the kwbimage
21 * Boot Device : one of
27 * Device Configuration Data (DCD)
29 * Each entry must have the format:
30 * Addr-type Address Value
33 * Addr-type register length (1,2 or 4 bytes)
34 * Address absolute address of the register
35 * value value to be stored in the register
40 #include "asm/arch/mx6-ddr.h"
41 #include "asm/arch/iomux.h"
42 #include "asm/arch/crm_regs.h"
44 DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
45 DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
46 DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
47 DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
48 DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
49 DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
50 DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
51 DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
53 DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
54 DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
55 DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
56 DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
57 DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
58 DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
59 DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
60 DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
62 DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
63 DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
64 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
65 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
67 DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
68 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
69 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
71 DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
73 DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
74 DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
76 DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
77 DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
78 DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
79 DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
80 DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
81 DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
82 DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
83 DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
84 DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
86 /* (differential input) */
87 DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
88 /* disable ddr pullups */
89 DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
90 /* (differential input) */
91 DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
92 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
93 DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
94 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
95 DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
97 /* Read data DQ Byte0-3 delay */
98 DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
99 DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
100 DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
101 DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
102 DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
103 DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
104 DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
105 DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
108 * MDMISC mirroring interleaved (row/bank/col)
110 DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
112 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
113 DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
114 DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
115 DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
116 DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
117 DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
118 DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
119 DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
120 DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
121 DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
122 DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
123 DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
124 DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
125 DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
126 DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
127 DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
128 DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
129 DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
130 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
131 DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
132 DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
133 DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
134 DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
135 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
136 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
137 DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
138 DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
139 DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
140 DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
141 DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
142 DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
143 DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
144 DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
145 DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
146 DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
147 DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
148 DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
149 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
150 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
151 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
152 DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
154 /* set the default clock gate to save power */
155 DATA 4, CCM_CCGR0, 0x00C03F3F
156 DATA 4, CCM_CCGR1, 0x0030FC03
157 DATA 4, CCM_CCGR2, 0x0FFFC000
158 DATA 4, CCM_CCGR3, 0x3FF00000
159 DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
160 DATA 4, CCM_CCGR5, 0x0F0000C3
161 DATA 4, CCM_CCGR6, 0x000003FF
163 /* enable AXI cache for VDOA/VPU/IPU */
164 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
165 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
166 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
167 DATA 4, MX6_IOMUXC_GPR7, 0x007F007F