2 * video.c - run splash screen on lcd
4 * Copyright (c) 2007-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/mach-common/bits/dma.h>
16 #include <linux/types.h>
17 #include <stdio_dev.h>
19 #include <asm/mach-common/bits/ppi.h>
20 #include <asm/mach-common/bits/timer.h>
22 #define LCD_X_RES 320 /* Horizontal Resolution */
23 #define LCD_Y_RES 240 /* Vertical Resolution */
24 #define DMA_BUS_SIZE 16
26 #ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 /* lq035q1 */
28 #if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
29 !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
30 # define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
33 /* Interface 16/18-bit TFT over an 8-bit wide PPI using a
34 * small Programmable Logic Device (CPLD)
35 * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
38 #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
39 #include <asm/bfin_logo_rgb565_230x230.h>
40 #define LCD_BPP 16 /* Bit Per Pixel */
41 #define CLOCKS_PPIX 2 /* Clocks per pixel */
42 #define CPLD_DELAY 3 /* RGB565 pipeline delay */
45 #ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
46 #include <asm/bfin_logo_230x230.h>
47 #define LCD_BPP 24 /* Bit Per Pixel */
48 #define CLOCKS_PPIX 3 /* Clocks per pixel */
49 #define CPLD_DELAY 5 /* RGB888 pipeline delay */
53 * HS and VS timing parameters (all in number of PPI clk ticks)
56 #define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
57 #define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
58 #define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
59 #define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
61 #define U_LINE 4 /* Blanking Lines */
63 #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
64 #define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
65 #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
67 #define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
72 #define LQ035_RL (0 << 8) /* Right -> Left Scan */
73 #define LQ035_LR (1 << 8) /* Left -> Right Scan */
74 #define LQ035_TB (1 << 9) /* Top -> Botton Scan */
75 #define LQ035_BT (0 << 9) /* Botton -> Top Scan */
76 #define LQ035_BGR (1 << 11) /* Use BGR format */
77 #define LQ035_RGB (0 << 11) /* Use RGB format */
78 #define LQ035_NORM (1 << 13) /* Reversal */
79 #define LQ035_REV (0 << 13) /* Reversal */
81 #define LQ035_INDEX 0x74
82 #define LQ035_DATA 0x76
84 #define LQ035_DRIVER_OUTPUT_CTL 0x1
85 #define LQ035_SHUT_CTL 0x11
87 #define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
88 #define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
90 #define LQ035_SHUT (1 << 0) /* Shutdown */
91 #define LQ035_ON (0 << 0) /* Shutdown */
93 #ifndef CONFIG_LQ035Q1_LCD_MODE
94 #define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
98 #include <asm/bfin_logo_230x230.h>
100 #define LCD_BPP 24 /* Bit Per Pixel */
101 #define CLOCKS_PPIX 3 /* Clocks per pixel */
103 /* HS and VS timing parameters (all in number of PPI clk ticks) */
104 #define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
105 #define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
106 #define H_PULSE 90 /* HS pulse width */
107 #define H_START 204 /* first valid pixel */
109 #define U_LINE 1 /* Blanking Lines */
111 #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
112 #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
113 #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
115 #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
118 #define LCD_PIXEL_SIZE (LCD_BPP / 8)
121 #define PPI_TX_MODE 0x2
122 #define PPI_XFER_TYPE_11 0xC
123 #define PPI_PORT_CFG_01 0x10
124 #define PPI_PACK_EN 0x80
125 #define PPI_POLS_1 0x8000
127 #ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
128 static struct spi_slave *slave;
129 static int lq035q1_control(unsigned char reg, unsigned short value)
132 u8 regs[3] = {LQ035_INDEX, 0, 0};
133 u8 data[3] = {LQ035_DATA, 0, 0};
137 data[1] = value >> 8;
138 data[2] = value & 0xFF;
141 /* FIXME: Verify the max SCK rate */
142 slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
143 CONFIG_LQ035Q1_SPI_CS, 20000000,
149 if (spi_claim_bus(slave))
152 ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
153 ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
155 spi_release_bus(slave);
161 /* enable and disable PPI functions */
164 *pPPI_CONTROL |= PORT_EN;
167 void DisablePPI(void)
169 *pPPI_CONTROL &= ~PORT_EN;
172 void Init_Ports(void)
174 *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
175 *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
176 *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
178 *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
179 *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
186 *pPPI_DELAY = H_START;
187 *pPPI_COUNT = (H_ACTPIX-1);
188 *pPPI_FRAME = V_LINES;
190 /* PPI control, to be replaced with definitions */
191 *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
192 PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
193 PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
194 PPI_PACK_EN | /* packing enabled PACK_EN */
195 PPI_POLS_1; /* faling edge syncs POLS */
198 void Init_DMA(void *dst)
200 *pDMA0_START_ADDR = dst;
203 *pDMA0_X_COUNT = H_ACTPIX / 2;
204 *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
207 *pDMA0_Y_COUNT = V_LINES;
208 *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
212 WDSIZE_16 | /* 16 bit DMA */
214 FLOW_AUTO; /* autobuffer mode */
220 *pDMA0_CONFIG |= DMAEN;
223 void DisableDMA(void)
225 *pDMA0_CONFIG &= ~DMAEN;
229 /* Init TIMER0 as Frame Sync 1 generator */
230 void InitTIMER0(void)
232 *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
234 *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
237 *pTIMER0_PERIOD = H_PERIOD;
239 *pTIMER0_WIDTH = H_PULSE;
242 *pTIMER0_CONFIG = PWM_OUT |
250 void EnableTIMER0(void)
252 *pTIMER_ENABLE |= TIMEN0;
256 void DisableTIMER0(void)
258 *pTIMER_DISABLE |= TIMDIS0;
263 void InitTIMER1(void)
265 *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
267 *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
271 *pTIMER1_PERIOD = V_PERIOD;
273 *pTIMER1_WIDTH = V_PULSE;
276 *pTIMER1_CONFIG = PWM_OUT |
284 void EnableTIMER1(void)
286 *pTIMER_ENABLE |= TIMEN1;
290 void DisableTIMER1(void)
292 *pTIMER_DISABLE |= TIMDIS1;
296 void EnableTIMER12(void)
298 *pTIMER_ENABLE |= TIMEN1 | TIMEN0;
302 int video_init(void *dst)
305 #ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
306 lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
307 lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
308 LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
318 #ifdef CONFIG_MK_BF527_EZKIT_REV_2_1
321 /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
323 /* Add Some Delay ... */
329 /* now start frame sync 1 */
336 static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
339 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
341 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
343 /* Setup destination start address */
344 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
345 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
346 /* Setup destination xcount */
347 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
348 /* Setup destination xmodify */
349 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
351 /* Setup destination ycount */
352 bfin_write_MDMA_D0_Y_COUNT(logo->height);
353 /* Setup destination ymodify */
354 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
357 /* Setup Source start address */
358 bfin_write_MDMA_S0_START_ADDR(logo->data);
359 /* Setup Source xcount */
360 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
361 /* Setup Source xmodify */
362 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
364 /* Setup Source ycount */
365 bfin_write_MDMA_S0_Y_COUNT(logo->height);
366 /* Setup Source ymodify */
367 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
370 /* Enable source DMA */
371 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
373 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
375 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
377 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
378 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
382 void video_putc(const char c)
386 void video_puts(const char *s)
390 int drv_video_init(void)
392 int error, devices = 1;
393 struct stdio_dev videodev;
396 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
398 dst = malloc(fbmem_size);
401 printf("Failed to alloc FB memory\n");
405 #ifdef EASYLOGO_ENABLE_GZIP
406 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
407 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
408 if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
409 puts("Failed to decompress logo\n");
413 bfin_logo.data = data;
416 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
418 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
419 (LCD_X_RES - bfin_logo.width) / 2,
420 (LCD_Y_RES - bfin_logo.height) / 2);
422 video_init(dst); /* Video initialization */
424 memset(&videodev, 0, sizeof(videodev));
426 strcpy(videodev.name, "video");
427 videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
428 videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
429 videodev.putc = video_putc; /* 'putc' function */
430 videodev.puts = video_puts; /* 'puts' function */
432 error = stdio_register(&videodev);
434 return (error == 0) ? devices : error;