2 #define NO_PHY_REGS 0x20
4 #define DEFAULT_PHY_PHYID1 0x0007
5 #define DEFAULT_PHY_PHYID2 0xC0A3
6 #define PHY_MODECTL 0x00
7 #define PHY_MODESTAT 0x01
8 #define PHY_PHYID1 0x02
9 #define PHY_PHYID2 0x03
11 #define PHY_ANLPAR 0x05
14 #define PHY_RESET 0x8000
15 #define PHY_ANEG_EN 0x1000
16 #define PHY_DUPLEX 0x0100
17 #define PHY_SPD_SET 0x2000
19 #define RECV_BUFSIZE (0x614)
21 typedef volatile u32 reg32;
22 typedef volatile u16 reg16;
24 typedef struct ADI_DMA_CONFIG_REG {
25 u16 b_DMA_EN:1; /* 0 Enabled */
26 u16 b_WNR:1; /* 1 Direction */
27 u16 b_WDSIZE:2; /* 2:3 Transfer word size */
28 u16 b_DMA2D:1; /* 4 DMA mode */
29 u16 b_RESTART:1; /* 5 Retain FIFO */
30 u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
31 u16 b_DI_EN:1; /* 7 Data interrupt enabled */
32 u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
33 u16 b_FLOW:3; /* 12:14Flow */
36 typedef struct adi_ether_frame_buffer {
37 u16 NoBytes; /* the no. of following bytes */
38 u8 Dest[6]; /* destination MAC address */
39 u8 Srce[6]; /* source MAC address */
40 u16 LTfield; /* length/type field */
41 u8 Data[0]; /* payload bytes */
42 } ADI_ETHER_FRAME_BUFFER;
45 typedef struct dma_descriptor {
46 struct dma_descriptor *NEXT_DESC_PTR;
48 ADI_DMA_CONFIG_REG CONFIG;
50 /* 10 bytes/struct in 12 bytes */
52 typedef struct adi_ether_buffer {
53 DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
54 ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
55 struct adi_ether_buffer *pNext; /* next buffer */
56 struct adi_ether_buffer *pPrev; /* prev buffer */
57 u16 IPHdrChksum; /* the IP header checksum */
58 u16 IPPayloadChksum; /* the IP header and payload checksum */
59 volatile u32 StatusWord; /* the frame status word */
61 /* 40 bytes/struct in 44 bytes */
63 void SetupMacAddr(u8 * MACaddr);
65 void PollMdcDone(void);
66 void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
67 u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
68 void SoftResetPHY(void);
69 void DumpPHYRegs(void);
71 int SetupSystemRegs(int *opmode);