4 * Board functions for Birdland Audio BAV335x Network Processor
6 * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
29 #include <power/tps65217.h>
30 #include <power/tps65910.h>
31 #include <environment.h>
33 #include <environment.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN 7
41 static __maybe_unused struct ctrl_dev *cdev =
42 (struct ctrl_dev *)CTRL_DEVICE_BASE;
47 * Read header information from EEPROM into global structure.
49 static int read_eeprom(struct board_eeconfig *header)
51 /* Check if baseboard eeprom is available */
52 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
55 /* read the eeprom using i2c */
56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
57 sizeof(struct board_eeconfig)))
60 if (header->magic != BOARD_MAGIC) {
61 /* read the i2c eeprom again using only a 1 byte address */
62 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
63 sizeof(struct board_eeconfig)))
66 if (header->magic != BOARD_MAGIC)
75 enum board_type get_board_type(bool debug)
78 struct board_eeconfig header;
80 ecode = read_eeprom(&header);
82 if (header.version[1] == 'A') {
84 puts("=== Detected Board model BAV335x Rev.A");
86 } else if (header.version[1] == 'B') {
88 puts("=== Detected Board model BAV335x Rev.B");
91 puts("### Un-known board model in serial-EE\n");
96 puts("### Board doesn't have a serial-EE\n");
99 puts("### Board serial-EE signature is incorrect.\n");
102 puts("### IO Error reading serial-EE.\n");
107 #if (CONFIG_BAV_VERSION == 1)
109 puts("### Selecting BAV335A as per config\n");
111 #elif (CONFIG_BAV_VERSION == 2)
113 puts("### Selecting BAV335B as per config\n");
116 #if (NOT_DEFINED == 2)
117 #error "SHOULD NEVER DISPLAY THIS"
121 puts("### Defaulting to model BAV335x Rev.B\n");
127 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
128 static const struct ddr_data ddr3_bav335x_data = {
129 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
130 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
131 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
132 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
135 static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
136 .cmd0csratio = MT41K256M16HA125E_RATIO,
137 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
138 .cmd1csratio = MT41K256M16HA125E_RATIO,
139 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
140 .cmd2csratio = MT41K256M16HA125E_RATIO,
141 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
145 static struct emif_regs ddr3_bav335x_emif_reg_data = {
146 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
147 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
148 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
149 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
150 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
151 .zq_config = MT41K256M16HA125E_ZQ_CFG,
152 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
156 #ifdef CONFIG_SPL_OS_BOOT
157 int spl_start_uboot(void)
159 /* break into full u-boot on 'c' */
160 if (serial_tstc() && serial_getc() == 'c')
163 #ifdef CONFIG_SPL_ENV_SUPPORT
166 if (getenv_yesno("boot_os") != 1)
174 #define OSC (V_OSCK/1000000)
175 const struct dpll_params dpll_ddr = {
176 266, OSC-1, 1, -1, -1, -1, -1};
177 const struct dpll_params dpll_ddr_evm_sk = {
178 303, OSC-1, 1, -1, -1, -1, -1};
179 const struct dpll_params dpll_ddr_bone_black = {
180 400, OSC-1, 1, -1, -1, -1, -1};
182 void am33xx_spl_board_init(void)
184 /* debug print detect status */
185 (void)get_board_type(true);
187 /* Get the frequency */
188 /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
189 dpll_mpu_opp100.m = MPUPLL_M_1000;
191 if (i2c_probe(TPS65217_CHIP_PM))
194 /* Set the USB Current Limit */
195 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
196 TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
197 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
198 puts("! tps65217_reg_write: could not set USB limit\n");
200 /* Set the Core Voltage (DCDC3) to 1.125V */
201 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
202 TPS65217_DCDC_VOLT_SEL_1125MV)) {
203 puts("! tps65217_reg_write: could not set Core Voltage\n");
207 /* Set CORE Frequencies to OPP100 */
208 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
210 /* Set the MPU Voltage (DCDC2) */
211 if (tps65217_voltage_update(TPS65217_DEFDCDC2,
212 TPS65217_DCDC_VOLT_SEL_1325MV)) {
213 puts("! tps65217_reg_write: could not set MPU Voltage\n");
218 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
219 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
221 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
222 TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
223 puts("! tps65217_reg_write: could not set LDO3\n");
225 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
226 TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
227 puts("! tps65217_reg_write: could not set LDO4\n");
229 /* Set MPU Frequency to what we detected now that voltages are set */
230 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
233 const struct dpll_params *get_dpll_ddr_params(void)
235 enable_i2c0_pin_mux();
236 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
238 return &dpll_ddr_bone_black;
241 void set_uart_mux_conf(void)
243 #if CONFIG_CONS_INDEX == 1
244 enable_uart0_pin_mux();
245 #elif CONFIG_CONS_INDEX == 2
246 enable_uart1_pin_mux();
247 #elif CONFIG_CONS_INDEX == 3
248 enable_uart2_pin_mux();
249 #elif CONFIG_CONS_INDEX == 4
250 enable_uart3_pin_mux();
251 #elif CONFIG_CONS_INDEX == 5
252 enable_uart4_pin_mux();
253 #elif CONFIG_CONS_INDEX == 6
254 enable_uart5_pin_mux();
258 void set_mux_conf_regs(void)
260 enum board_type board;
262 board = get_board_type(false);
263 enable_board_pin_mux(board);
266 const struct ctrl_ioregs ioregs_bonelt = {
267 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
268 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
269 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
270 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
271 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
275 void sdram_init(void)
277 config_ddr(400, &ioregs_bonelt,
279 &ddr3_bav335x_cmd_ctrl_data,
280 &ddr3_bav335x_emif_reg_data, 0);
285 * Basic board specific setup. Pinmux has been handled already.
289 #if defined(CONFIG_HW_WATCHDOG)
293 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
294 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
300 #ifdef CONFIG_BOARD_LATE_INIT
301 int board_late_init(void)
303 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
304 setenv("board_name", "BAV335xB");
305 setenv("board_rev", "B"); /* Fix me, but why bother.. */
312 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
313 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
314 static void cpsw_control(int enabled)
316 /* VTP can be added here */
320 static struct cpsw_slave_data cpsw_slaves[] = {
322 .slave_reg_ofs = 0x208,
323 .sliver_reg_ofs = 0xd80,
327 .slave_reg_ofs = 0x308,
328 .sliver_reg_ofs = 0xdc0,
333 static struct cpsw_platform_data cpsw_data = {
334 .mdio_base = CPSW_MDIO_BASE,
335 .cpsw_base = CPSW_BASE,
338 .cpdma_reg_ofs = 0x800,
340 .slave_data = cpsw_slaves,
341 .ale_reg_ofs = 0xd00,
343 .host_port_reg_ofs = 0x108,
344 .hw_stats_reg_ofs = 0x900,
345 .bd_ram_ofs = 0x2000,
346 .mac_control = (1 << 5),
347 .control = cpsw_control,
349 .version = CPSW_CTRL_VERSION_2,
355 * This function will:
356 * Perform fixups to the PHY present on certain boards. We only need this
358 * - SPL with either CPSW or USB ethernet support
359 * - Full U-Boot, with either CPSW or USB ethernet
360 * Build in only these cases to avoid warnings about unused variables
361 * when we build an SPL that has neither option but full U-Boot will.
363 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
364 defined(CONFIG_SPL_BUILD)) || \
365 ((defined(CONFIG_DRIVER_TI_CPSW) || \
366 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
367 !defined(CONFIG_SPL_BUILD))
368 int board_eth_init(bd_t *bis)
372 struct board_eeconfig header;
373 __maybe_unused enum board_type board;
375 /* Default manufacturing address; used when no EE or invalid */
384 ecode = read_eeprom(&header);
385 /* if we have a valid EE, get mac address from there */
387 is_valid_ether_addr((const u8 *)&header.mac_addr[0][0])) {
388 memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
392 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
393 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
395 if (!getenv("ethaddr")) {
396 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
398 if (is_valid_ether_addr(mac_addr))
399 eth_setenv_enetaddr("ethaddr", mac_addr);
402 #ifdef CONFIG_DRIVER_TI_CPSW
404 board = get_board_type(false);
406 /* Rev.A uses 10/100 PHY in mii mode */
407 if (board == BAV335A) {
408 writel(MII_MODE_ENABLE, &cdev->miisel);
409 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
410 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
412 /* Rev.B (default) uses GB PHY in rmii mode */
414 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
415 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
416 = PHY_INTERFACE_MODE_RGMII;
419 rv = cpsw_register(&cpsw_data);
421 printf("Error %d registering CPSW switch\n", rv);