1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Boundary Devices
5 * Device Configuration Data (DCD)
7 * Each entry must have the format:
8 * Addr-type Address Value
11 * Addr-type register length (1,2 or 4 bytes)
12 * Address absolute address of the register
13 * value value to be stored in the register
16 /* set the default clock gate to save power */
17 DATA 4, CCM_CCGR0, 0x00C03F3F
18 DATA 4, CCM_CCGR1, 0x0030FC03
19 DATA 4, CCM_CCGR2, 0x0FFFC000
20 DATA 4, CCM_CCGR3, 0x3FF00000
21 DATA 4, CCM_CCGR4, 0x00FFF300
22 DATA 4, CCM_CCGR5, 0x0F0000C3
23 DATA 4, CCM_CCGR6, 0x000003FF
25 /* enable AXI cache for VDOA/VPU/IPU */
26 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
27 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
28 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
29 DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
32 * Setup CCM_CCOSR register as follows:
34 * cko1_en = 1 --> CKO1 enabled
35 * cko1_div = 111 --> divide by 8
36 * cko1_sel = 1011 --> ahb_clk_root
38 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
40 DATA 4, CCM_CCOSR, 0x000000fb