2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
7 * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/at91sam9260_matrix.h>
31 #include <asm/arch/at91sam9_smc.h>
32 #include <asm/arch/at91_common.h>
33 #include <asm/arch/at91_pmc.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/gpio.h>
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
42 DECLARE_GLOBAL_DATA_PTR;
44 /* ------------------------------------------------------------------------- */
46 * Miscelaneous platform dependent initialisations
49 #ifdef CONFIG_CMD_NAND
50 static void sbc35_a9g20_nand_hw_init(void)
52 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
53 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
54 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
58 csa = readl(&matrix->ebicsa);
59 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
60 writel(csa, &matrix->ebicsa);
62 /* Configure SMC CS3 for NAND/SmartMedia */
63 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
64 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
66 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
67 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
69 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
71 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
72 AT91_SMC_MODE_EXNW_DISABLE |
73 #ifdef CONFIG_SYS_NAND_DBW_16
74 AT91_SMC_MODE_DBW_16 |
75 #else /* CONFIG_SYS_NAND_DBW_8 */
78 AT91_SMC_MODE_TDF_CYCLE(2),
81 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
83 /* Configure RDY/BSY */
84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
86 /* Enable NandFlash */
87 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
92 static void sbc35_a9g20_macb_hw_init(void)
94 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
95 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
96 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
99 /* Enable EMAC clock */
100 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
103 * Disable pull-up on:
104 * RXDV (PA17) => PHY normal mode (not Test mode)
105 * ERX0 (PA14) => PHY ADDR0
106 * ERX1 (PA15) => PHY ADDR1
107 * ERX2 (PA25) => PHY ADDR2
108 * ERX3 (PA26) => PHY ADDR3
109 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
111 * PHY has internal pull-down
113 writel(pin_to_mask(AT91_PIN_PA14) |
114 pin_to_mask(AT91_PIN_PA15) |
115 pin_to_mask(AT91_PIN_PA17) |
116 pin_to_mask(AT91_PIN_PA25) |
117 pin_to_mask(AT91_PIN_PA26) |
118 pin_to_mask(AT91_PIN_PA28),
121 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
123 /* Need to reset PHY -> 500ms reset */
124 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
125 AT91_RSTC_MR_URSTEN, &rstc->mr);
127 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
129 /* Wait for end hardware reset */
130 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
133 /* Restore NRST value */
134 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
137 /* Re-enable pull-up */
138 writel(pin_to_mask(AT91_PIN_PA14) |
139 pin_to_mask(AT91_PIN_PA15) |
140 pin_to_mask(AT91_PIN_PA17) |
141 pin_to_mask(AT91_PIN_PA25) |
142 pin_to_mask(AT91_PIN_PA26) |
143 pin_to_mask(AT91_PIN_PA28),
152 /* adress of boot parameters */
153 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
155 at91_seriald_hw_init();
156 sbc35_a9g20_nand_hw_init();
157 #ifdef CONFIG_ATMEL_SPI
158 at91_spi0_hw_init(1 << 4 | 1 << 5);
161 sbc35_a9g20_macb_hw_init();
169 gd->ram_size = get_ram_size(
170 (void *)CONFIG_SYS_SDRAM_BASE,
171 CONFIG_SYS_SDRAM_SIZE);
175 #ifdef CONFIG_RESET_PHY_R
181 int board_eth_init(bd_t *bis)
185 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);