git.sur5r.net Git - u-boot/blob - board/ccv/xpress/xpress.c

   1 /*
   2  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/mx6ul_pins.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/io.h>
  19 #include <common.h>
  20 #include <fsl_esdhc.h>
  21 #include <i2c.h>
  22 #include <miiphy.h>
  23 #include <mmc.h>
  24 #include <netdev.h>
  25 #include <usb.h>
  26 #include <usb/ehci-ci.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  31         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  32         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  35         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  36         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  39         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  40         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  41         PAD_CTL_ODE)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  44         PAD_CTL_SPEED_HIGH   |                                  \
  45         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  46
  47 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  48         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  49
  50 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  51
  52 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  53         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  54
  55 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |                \
  57         PAD_CTL_DSE_80ohm | PAD_CTL_HYS |                       \
  58         PAD_CTL_SRE_FAST)
  59
  60 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  61
  62 static struct i2c_pads_info i2c_pad_info1 = {
  63         .scl = {
  64                 .i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  65                 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  66                 .gp = IMX_GPIO_NR(1, 2),
  67         },
  68         .sda = {
  69                 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  70                 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  71                 .gp = IMX_GPIO_NR(1, 3),
  72         },
  73 };
  74
  75 static struct i2c_pads_info i2c_pad_info2 = {
  76         .scl = {
  77                 .i2c_mode =  MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
  78                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
  79                 .gp = IMX_GPIO_NR(1, 0),
  80         },
  81         .sda = {
  82                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
  83                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
  84                 .gp = IMX_GPIO_NR(1, 1),
  85         },
  86 };
  87
  88 static struct i2c_pads_info i2c_pad_info4 = {
  89         .scl = {
  90                 .i2c_mode =  MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
  91                 .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC,
  92                 .gp = IMX_GPIO_NR(1, 20),
  93         },
  94         .sda = {
  95                 .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC,
  96                 .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC,
  97                 .gp = IMX_GPIO_NR(1, 21),
  98         },
  99 };
 100
 101 int dram_init(void)
 102 {
 103         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 104
 105         return 0;
 106 }
 107
 108 static iomux_v3_cfg_t const uart1_pads[] = {
 109         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 110         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 111         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 112         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 113 };
 114
 115 static iomux_v3_cfg_t const uart4_pads[] = {
 116         MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 117         MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 118 };
 119
 120 static iomux_v3_cfg_t const uart5_pads[] = {
 121         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 122         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 123         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 124         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 125 };
 126
 127 static iomux_v3_cfg_t const uart7_pads[] = {
 128         MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 129         MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 130 };
 131
 132 static iomux_v3_cfg_t const uart8_pads[] = {
 133         MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 134         MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 135 };
 136
 137 static void setup_iomux_uart(void)
 138 {
 139         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 140         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 141         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 142         imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 143         imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
 144 }
 145
 146 /* eMMC on USDHC2 */
 147 static iomux_v3_cfg_t const usdhc2_pads[] = {
 148         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 152         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 153         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 154         MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 155         MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 156         MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 157         MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 158
 159         /*
 160          * RST_B
 161          */
 162         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 163 };
 164
 165 static struct fsl_esdhc_cfg usdhc_cfg = {
 166         .esdhc_base = USDHC2_BASE_ADDR,
 167         .max_bus_width = 8,
 168 };
 169
 170 #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
 171
 172 int board_mmc_getcd(struct mmc *mmc)
 173 {
 174         /* eMMC is always present */
 175         return 1;
 176 }
 177
 178 int board_mmc_init(bd_t *bis)
 179 {
 180         imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 181
 182         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 183
 184         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 185 }
 186
 187 #define USB_OTHERREGS_OFFSET    0x800
 188 #define UCTRL_PWR_POL           (1 << 9)
 189
 190 static iomux_v3_cfg_t const usb_otg_pads[] = {
 191         /* OTG1 */
 192         MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 193         MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 194         /* OTG2 */
 195         MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 196         MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
 197 };
 198
 199 static void setup_usb(void)
 200 {
 201         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 202                                          ARRAY_SIZE(usb_otg_pads));
 203 }
 204
 205 int board_usb_phy_mode(int port)
 206 {
 207         if (port == 1)
 208                 return USB_INIT_HOST;
 209         else
 210                 return usb_phy_mode(port);
 211 }
 212
 213 int board_ehci_hcd_init(int port)
 214 {
 215         u32 *usbnc_usb_ctrl;
 216
 217         if (port > 1)
 218                 return -EINVAL;
 219
 220         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 221                                  port * 4);
 222
 223         /* Set Power polarity */
 224         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 225
 226         return 0;
 227 }
 228
 229 static iomux_v3_cfg_t const fec1_pads[] = {
 230         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
 231         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 236         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 238         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 240
 241         /* ENET1 reset */
 242         MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
 243         /* ENET1 interrupt */
 244         MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 245 };
 246
 247 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
 248
 249 int board_eth_init(bd_t *bis)
 250 {
 251         int ret;
 252
 253         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 254
 255         /* Reset LAN8742 PHY */
 256         ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
 257         if (!ret)
 258                 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
 259         mdelay(10);
 260         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 261         mdelay(10);
 262
 263         return cpu_eth_init(bis);
 264 }
 265
 266 static int setup_fec(int fec_id)
 267 {
 268         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 269         int ret;
 270
 271         /*
 272          * Use 50M anatop loopback REF_CLK1 for ENET1,
 273          * clear gpr1[13], set gpr1[17].
 274          */
 275         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
 276                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
 277
 278         ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
 279         if (ret)
 280                 return ret;
 281
 282         enable_enet_clk(1);
 283
 284         return 0;
 285 }
 286
 287 int board_phy_config(struct phy_device *phydev)
 288 {
 289         if (phydev->drv->config)
 290                 phydev->drv->config(phydev);
 291
 292         return 0;
 293 }
 294
 295 int board_early_init_f(void)
 296 {
 297         setup_iomux_uart();
 298
 299         return 0;
 300 }
 301
 302 int board_init(void)
 303 {
 304         /* Address of boot parameters */
 305         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 306
 307         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 308         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 309         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 310
 311         setup_fec(CONFIG_FEC_ENET_DEV);
 312
 313         setup_usb();
 314
 315         return 0;
 316 }
 317
 318 static const struct boot_mode board_boot_modes[] = {
 319         /* 8 bit bus width */
 320         {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
 321         { NULL, 0 },
 322 };
 323
 324 int board_late_init(void)
 325 {
 326         add_board_boot_modes(board_boot_modes);
 327         env_set("board_name", "xpress");
 328
 329         return 0;
 330 }
 331
 332 int checkboard(void)
 333 {
 334         puts("Board: CCV-EVA xPress\n");
 335
 336         return 0;
 337 }