2 * Copyright 2006 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* Config the VIA chip */
27 void mpc85xx_config_via(struct pci_controller *hose,
28 pci_dev_t dev, struct pci_config_table *tab)
32 /* Enable USB and IDE functions */
33 pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
35 pciauto_config_device(hose, dev);
38 * Force the backplane P2P bridge to have a window
39 * open from 0x00000000-0x00001fff in PCI I/O space.
40 * This allows legacy I/O (i8259, etc) on the VIA
41 * southbridge to be accessed.
43 bridge = PCI_BDF(0,17,0);
44 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
45 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
46 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
47 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
51 void mpc85xx_config_via_usbide(struct pci_controller *hose,
52 pci_dev_t dev, struct pci_config_table *tab)
54 pciauto_config_device(hose, dev);
56 * Since the P2P window was forced to cover the fixed
57 * legacy I/O addresses, it is necessary to manually
58 * place the base addresses for the IDE and USB functions
61 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
62 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
63 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
64 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
65 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
68 /* Function 2, USB ports 0-1 */
69 void mpc85xx_config_via_usb(struct pci_controller *hose,
70 pci_dev_t dev, struct pci_config_table *tab)
72 pciauto_config_device(hose, dev);
74 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
77 /* Function 3, USB ports 2-3 */
78 void mpc85xx_config_via_usb2(struct pci_controller *hose,
79 pci_dev_t dev, struct pci_config_table *tab)
81 pciauto_config_device(hose, dev);
83 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
86 /* Function 5, Power Management */
87 void mpc85xx_config_via_power(struct pci_controller *hose,
88 pci_dev_t dev, struct pci_config_table *tab)
90 pciauto_config_device(hose, dev);
92 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
93 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
94 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
97 /* Function 6, AC97 Interface */
98 void mpc85xx_config_via_ac97(struct pci_controller *hose,
99 pci_dev_t dev, struct pci_config_table *tab)
101 pciauto_config_device(hose, dev);
103 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);