2 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
32 #include "../common/cadmus.h"
33 #include "../common/eeprom.h"
34 #include "../common/via.h"
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 extern long int spd_sdram(void);
42 void local_bus_init(void);
43 void sdram_init(void);
45 int board_early_init_f (void)
52 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
53 volatile ccsr_gur_t *gur = &immap->im_gur;
55 /* PCI slot in USER bits CSR[6:7] by convention. */
56 uint pci_slot = get_pci_slot ();
58 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
59 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
60 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
61 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
63 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
65 uint cpu_board_rev = get_cpu_board_revision ();
67 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
68 get_board_version (), pci_slot);
70 printf ("CPU Board Revision %d.%d (0x%04x)\n",
71 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
72 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
74 printf (" PCI1: %d bit, %s MHz, %s\n",
76 (pci1_speed == 33000000) ? "33" :
77 (pci1_speed == 66000000) ? "66" : "unknown",
78 pci1_clk_sel ? "sync" : "async");
81 printf (" PCI2: 32 bit, 66 MHz, %s\n",
82 pci2_clk_sel ? "sync" : "async");
84 printf (" PCI2: disabled\n");
88 * Initialize local bus.
94 * Hack TSEC 3 and 4 IO voltages.
96 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
102 initdram(int board_type)
105 volatile immap_t *immap = (immap_t *)CFG_IMMR;
107 puts("Initializing\n");
109 #if defined(CONFIG_DDR_DLL)
112 * Work around to stabilize DDR DLL MSYNC_IN.
113 * Errata DDR9 seems to have been fixed.
114 * This is now the workaround for Errata DDR11:
115 * Override DLL = 1, Course Adj = 1, Tap Select = 0
118 volatile ccsr_gur_t *gur= &immap->im_gur;
120 gur->ddrdllcr = 0x81000000;
121 asm("sync;isync;msync");
125 dram_size = spd_sdram();
127 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
129 * Initialize and enable DDR ECC.
131 ddr_enable_ecc(dram_size);
134 * SDRAM Initialization
143 * Initialize Local Bus
148 volatile immap_t *immap = (immap_t *)CFG_IMMR;
149 volatile ccsr_gur_t *gur = &immap->im_gur;
150 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
156 get_sys_info(&sysinfo);
157 clkdiv = (lbc->lcrr & 0x0f) * 2;
158 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
160 gur->lbiuiplldcr1 = 0x00078080;
162 gur->lbiuiplldcr0 = 0x7c0f1bf0;
163 } else if (clkdiv == 8) {
164 gur->lbiuiplldcr0 = 0x6c0f1bf0;
165 } else if (clkdiv == 4) {
166 gur->lbiuiplldcr0 = 0x5c0f1bf0;
169 lbc->lcrr |= 0x00030000;
171 asm("sync;isync;msync");
175 * Initialize SDRAM memory on the Local Bus.
180 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
183 volatile immap_t *immap = (immap_t *)CFG_IMMR;
184 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
185 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
191 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
194 * Setup SDRAM Base and Option Registers
196 lbc->or2 = CFG_OR2_PRELIM;
199 lbc->br2 = CFG_BR2_PRELIM;
202 lbc->lbcr = CFG_LBC_LBCR;
206 lbc->lsrt = CFG_LBC_LSRT;
207 lbc->mrtpr = CFG_LBC_MRTPR;
211 * MPC8548 uses "new" 15-16 style addressing.
213 cpu_board_rev = get_cpu_board_revision();
214 lsdmr_common = CFG_LBC_LSDMR_COMMON;
215 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
218 * Issue PRECHARGE ALL command.
220 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
223 ppcDcbf((unsigned long) sdram_addr);
227 * Issue 8 AUTO REFRESH commands.
229 for (idx = 0; idx < 8; idx++) {
230 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
233 ppcDcbf((unsigned long) sdram_addr);
238 * Issue 8 MODE-set command.
240 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
243 ppcDcbf((unsigned long) sdram_addr);
247 * Issue NORMAL OP command.
249 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
252 ppcDcbf((unsigned long) sdram_addr);
253 udelay(200); /* Overkill. Must wait > 200 bus cycles */
255 #endif /* enable SDRAM init */
258 #if defined(CFG_DRAM_TEST)
262 uint *pstart = (uint *) CFG_MEMTEST_START;
263 uint *pend = (uint *) CFG_MEMTEST_END;
266 printf("Testing DRAM from 0x%08x to 0x%08x\n",
270 printf("DRAM test phase 1:\n");
271 for (p = pstart; p < pend; p++)
274 for (p = pstart; p < pend; p++) {
275 if (*p != 0xaaaaaaaa) {
276 printf ("DRAM test fails at: %08x\n", (uint) p);
281 printf("DRAM test phase 2:\n");
282 for (p = pstart; p < pend; p++)
285 for (p = pstart; p < pend; p++) {
286 if (*p != 0x55555555) {
287 printf ("DRAM test fails at: %08x\n", (uint) p);
292 printf("DRAM test passed.\n");
297 #if defined(CONFIG_PCI)
298 /* For some reason the Tundra PCI bridge shows up on itself as a
299 * different device. Work around that by refusing to configure it.
301 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
303 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
304 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
305 {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
306 {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
307 {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
308 {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
309 {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
310 {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
313 static struct pci_controller hose[] = {
314 { config_table: pci_mpc85xxcds_config_table,},
315 #ifdef CONFIG_MPC85XX_PCI2
320 #endif /* CONFIG_PCI */
326 pci_mpc85xx_init(&hose);
330 int last_stage_init(void)
334 /* Change the resistors for the PHY */
335 /* This is needed to get the RGMII working for the 1.3+
337 if (get_board_version() == 0x13) {
338 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
339 TSEC1_PHY_ADDR, 29, 18);
341 miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
342 TSEC1_PHY_ADDR, 30, &temp);
344 temp = (temp & 0xf03f);
345 temp |= 2 << 9; /* 36 ohm */
346 temp |= 2 << 6; /* 39 ohm */
348 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
349 TSEC1_PHY_ADDR, 30, temp);
351 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
352 TSEC1_PHY_ADDR, 29, 3);
354 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
355 TSEC1_PHY_ADDR, 30, 0x8000);