2 * Copyright 2004 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
32 #include "../common/cadmus.h"
33 #include "../common/eeprom.h"
34 #include "../common/via.h"
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 extern long int spd_sdram(void);
42 void local_bus_init(void);
43 void sdram_init(void);
45 int board_early_init_f (void)
52 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
53 volatile ccsr_gur_t *gur = &immap->im_gur;
54 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
56 /* PCI slot in USER bits CSR[6:7] by convention. */
57 uint pci_slot = get_pci_slot ();
59 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
60 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
61 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
62 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
64 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
66 uint cpu_board_rev = get_cpu_board_revision ();
68 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
69 get_board_version (), pci_slot);
71 printf ("CPU Board Revision %d.%d (0x%04x)\n",
72 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
73 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
75 printf (" PCI1: %d bit, %s MHz, %s\n",
77 (pci1_speed == 33000000) ? "33" :
78 (pci1_speed == 66000000) ? "66" : "unknown",
79 pci1_clk_sel ? "sync" : "async");
82 printf (" PCI2: 32 bit, 66 MHz, %s\n",
83 pci2_clk_sel ? "sync" : "async");
85 printf (" PCI2: disabled\n");
89 * Initialize local bus.
94 * Fix CPU2 errata: A core hang possible while executing a
95 * msync instruction and a snoopable transaction from an I/O
96 * master tagged to make quick forward progress is present.
98 ecm->eebpcr |= (1 << 16);
101 * Hack TSEC 3 and 4 IO voltages.
103 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
109 initdram(int board_type)
112 volatile immap_t *immap = (immap_t *)CFG_IMMR;
114 puts("Initializing\n");
116 #if defined(CONFIG_DDR_DLL)
119 * Work around to stabilize DDR DLL MSYNC_IN.
120 * Errata DDR9 seems to have been fixed.
121 * This is now the workaround for Errata DDR11:
122 * Override DLL = 1, Course Adj = 1, Tap Select = 0
125 volatile ccsr_gur_t *gur= &immap->im_gur;
127 gur->ddrdllcr = 0x81000000;
128 asm("sync;isync;msync");
132 dram_size = spd_sdram();
134 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
136 * Initialize and enable DDR ECC.
138 ddr_enable_ecc(dram_size);
141 * SDRAM Initialization
150 * Initialize Local Bus
155 volatile immap_t *immap = (immap_t *)CFG_IMMR;
156 volatile ccsr_gur_t *gur = &immap->im_gur;
157 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
163 get_sys_info(&sysinfo);
164 clkdiv = (lbc->lcrr & 0x0f) * 2;
165 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
167 gur->lbiuiplldcr1 = 0x00078080;
169 gur->lbiuiplldcr0 = 0x7c0f1bf0;
170 } else if (clkdiv == 8) {
171 gur->lbiuiplldcr0 = 0x6c0f1bf0;
172 } else if (clkdiv == 4) {
173 gur->lbiuiplldcr0 = 0x5c0f1bf0;
176 lbc->lcrr |= 0x00030000;
178 asm("sync;isync;msync");
182 * Initialize SDRAM memory on the Local Bus.
187 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
190 volatile immap_t *immap = (immap_t *)CFG_IMMR;
191 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
192 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
198 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
201 * Setup SDRAM Base and Option Registers
203 lbc->or2 = CFG_OR2_PRELIM;
206 lbc->br2 = CFG_BR2_PRELIM;
209 lbc->lbcr = CFG_LBC_LBCR;
213 lbc->lsrt = CFG_LBC_LSRT;
214 lbc->mrtpr = CFG_LBC_MRTPR;
218 * MPC8548 uses "new" 15-16 style addressing.
220 cpu_board_rev = get_cpu_board_revision();
221 lsdmr_common = CFG_LBC_LSDMR_COMMON;
222 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
225 * Issue PRECHARGE ALL command.
227 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
230 ppcDcbf((unsigned long) sdram_addr);
234 * Issue 8 AUTO REFRESH commands.
236 for (idx = 0; idx < 8; idx++) {
237 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
240 ppcDcbf((unsigned long) sdram_addr);
245 * Issue 8 MODE-set command.
247 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
250 ppcDcbf((unsigned long) sdram_addr);
254 * Issue NORMAL OP command.
256 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
259 ppcDcbf((unsigned long) sdram_addr);
260 udelay(200); /* Overkill. Must wait > 200 bus cycles */
262 #endif /* enable SDRAM init */
265 #if defined(CFG_DRAM_TEST)
269 uint *pstart = (uint *) CFG_MEMTEST_START;
270 uint *pend = (uint *) CFG_MEMTEST_END;
273 printf("Testing DRAM from 0x%08x to 0x%08x\n",
277 printf("DRAM test phase 1:\n");
278 for (p = pstart; p < pend; p++)
281 for (p = pstart; p < pend; p++) {
282 if (*p != 0xaaaaaaaa) {
283 printf ("DRAM test fails at: %08x\n", (uint) p);
288 printf("DRAM test phase 2:\n");
289 for (p = pstart; p < pend; p++)
292 for (p = pstart; p < pend; p++) {
293 if (*p != 0x55555555) {
294 printf ("DRAM test fails at: %08x\n", (uint) p);
299 printf("DRAM test passed.\n");
304 #if defined(CONFIG_PCI)
305 /* For some reason the Tundra PCI bridge shows up on itself as a
306 * different device. Work around that by refusing to configure it.
308 void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
310 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
311 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
312 {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
313 {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
314 mpc85xx_config_via_usbide, {0,0,0}},
315 {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
316 {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
317 {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
318 mpc85xx_config_via_power, {0,0,0}},
319 {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
323 static struct pci_controller hose[] = {
324 { config_table: pci_mpc85xxcds_config_table,},
325 #ifdef CONFIG_MPC85XX_PCI2
330 #endif /* CONFIG_PCI */
336 pci_mpc85xx_init(&hose);
340 int last_stage_init(void)
344 /* Change the resistors for the PHY */
345 /* This is needed to get the RGMII working for the 1.3+
347 if (get_board_version() == 0x13) {
348 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
349 TSEC1_PHY_ADDR, 29, 18);
351 miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
352 TSEC1_PHY_ADDR, 30, &temp);
354 temp = (temp & 0xf03f);
355 temp |= 2 << 9; /* 36 ohm */
356 temp |= 2 << 6; /* 39 ohm */
358 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
359 TSEC1_PHY_ADDR, 30, temp);
361 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
362 TSEC1_PHY_ADDR, 29, 3);
364 miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
365 TSEC1_PHY_ADDR, 30, 0x8000);