2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_85xx.h>
30 #include "../common/cadmus.h"
31 #include "../common/eeprom.h"
33 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
34 extern void ddr_enable_ecc(unsigned int dram_size);
37 extern long int spd_sdram(void);
39 void local_bus_init(void);
40 void sdram_init(void);
43 * I/O Port configuration table
45 * if conf is 1, then that port pin will be configured at boot time
46 * according to the five values podr/pdir/ppar/psor/pdat for that entry
49 const iop_conf_t iop_conf_tab[4][32] = {
51 /* Port A configuration */
52 { /* conf ppar psor pdir podr pdat */
53 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
54 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
55 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
56 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
57 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
58 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
59 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
60 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
61 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
62 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
63 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
64 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
65 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
66 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
67 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
68 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
69 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
70 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
71 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
72 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
73 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
74 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
75 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
76 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
77 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
78 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
79 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
80 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
81 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
82 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
83 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
84 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
87 /* Port B configuration */
88 { /* conf ppar psor pdir podr pdat */
89 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
90 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
91 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
92 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
93 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
94 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
95 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
96 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
97 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
98 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
99 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
100 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
101 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
102 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
103 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
104 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
105 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
106 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
107 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
108 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
109 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
110 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
114 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 { /* conf ppar psor pdir podr pdat */
125 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
126 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
127 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
128 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
129 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
130 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
131 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
132 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
133 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
134 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
135 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
136 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
137 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
138 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
139 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
140 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
141 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
142 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
143 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
144 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
145 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
146 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
147 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
148 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
149 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
150 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
151 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
152 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
153 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
154 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
155 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
156 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
160 { /* conf ppar psor pdir podr pdat */
161 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
162 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
163 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
164 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
165 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
166 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
167 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
168 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
169 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
170 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
171 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
172 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
173 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
174 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
175 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
176 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
177 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
178 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
179 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
180 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
181 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
182 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
183 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
184 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
185 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
186 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
187 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
188 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
189 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 int board_early_init_f (void)
201 int checkboard (void)
203 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
204 volatile ccsr_gur_t *gur = &immap->im_gur;
206 /* PCI slot in USER bits CSR[6:7] by convention. */
207 uint pci_slot = get_pci_slot ();
209 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
210 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
211 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
212 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
214 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
216 uint cpu_board_rev = get_cpu_board_revision ();
218 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
219 get_board_version (), pci_slot);
221 printf ("CPU Board Revision %d.%d (0x%04x)\n",
222 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
223 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
225 printf (" PCI1: %d bit, %s MHz, %s\n",
227 (pci1_speed == 33000000) ? "33" :
228 (pci1_speed == 66000000) ? "66" : "unknown",
229 pci1_clk_sel ? "sync" : "async");
232 printf (" PCI2: 32 bit, 66 MHz, %s\n",
233 pci2_clk_sel ? "sync" : "async");
235 printf (" PCI2: disabled\n");
239 * Initialize local bus.
247 initdram(int board_type)
250 volatile immap_t *immap = (immap_t *)CFG_IMMR;
252 puts("Initializing\n");
254 #if defined(CONFIG_DDR_DLL)
257 * Work around to stabilize DDR DLL MSYNC_IN.
258 * Errata DDR9 seems to have been fixed.
259 * This is now the workaround for Errata DDR11:
260 * Override DLL = 1, Course Adj = 1, Tap Select = 0
263 volatile ccsr_gur_t *gur= &immap->im_gur;
265 gur->ddrdllcr = 0x81000000;
266 asm("sync;isync;msync");
270 dram_size = spd_sdram();
272 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
274 * Initialize and enable DDR ECC.
276 ddr_enable_ecc(dram_size);
279 * SDRAM Initialization
288 * Initialize Local Bus
293 volatile immap_t *immap = (immap_t *)CFG_IMMR;
294 volatile ccsr_gur_t *gur = &immap->im_gur;
295 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
304 * Fix Local Bus clock glitch when DLL is enabled.
306 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
307 * If localbus freq is > 133Mhz, DLL can be safely enabled.
308 * Between 66 and 133, the DLL is enabled with an override workaround.
311 get_sys_info(&sysinfo);
312 clkdiv = lbc->lcrr & 0x0f;
313 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
316 lbc->lcrr |= 0x80000000; /* DLL Bypass */
318 } else if (lbc_hz >= 133) {
319 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
322 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
326 * Sample LBC DLL ctrl reg, upshift it to set the
329 temp_lbcdll = gur->lbcdllcr;
330 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
331 asm("sync;isync;msync");
336 * Initialize SDRAM memory on the Local Bus.
341 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
344 volatile immap_t *immap = (immap_t *)CFG_IMMR;
345 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
346 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
352 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
355 * Setup SDRAM Base and Option Registers
357 lbc->or2 = CFG_OR2_PRELIM;
360 lbc->br2 = CFG_BR2_PRELIM;
363 lbc->lbcr = CFG_LBC_LBCR;
366 lbc->lsrt = CFG_LBC_LSRT;
367 lbc->mrtpr = CFG_LBC_MRTPR;
371 * Determine which address lines to use baed on CPU board rev.
373 cpu_board_rev = get_cpu_board_revision();
374 lsdmr_common = CFG_LBC_LSDMR_COMMON;
375 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
376 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
377 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
378 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
381 * Assume something unable to identify itself is
382 * really old, and likely has lines 16/17 mapped.
384 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
388 * Issue PRECHARGE ALL command.
390 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
393 ppcDcbf((unsigned long) sdram_addr);
397 * Issue 8 AUTO REFRESH commands.
399 for (idx = 0; idx < 8; idx++) {
400 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
403 ppcDcbf((unsigned long) sdram_addr);
408 * Issue 8 MODE-set command.
410 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
413 ppcDcbf((unsigned long) sdram_addr);
417 * Issue NORMAL OP command.
419 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
422 ppcDcbf((unsigned long) sdram_addr);
423 udelay(200); /* Overkill. Must wait > 200 bus cycles */
425 #endif /* enable SDRAM init */
428 #if defined(CFG_DRAM_TEST)
432 uint *pstart = (uint *) CFG_MEMTEST_START;
433 uint *pend = (uint *) CFG_MEMTEST_END;
436 printf("Testing DRAM from 0x%08x to 0x%08x\n",
440 printf("DRAM test phase 1:\n");
441 for (p = pstart; p < pend; p++)
444 for (p = pstart; p < pend; p++) {
445 if (*p != 0xaaaaaaaa) {
446 printf ("DRAM test fails at: %08x\n", (uint) p);
451 printf("DRAM test phase 2:\n");
452 for (p = pstart; p < pend; p++)
455 for (p = pstart; p < pend; p++) {
456 if (*p != 0x55555555) {
457 printf ("DRAM test fails at: %08x\n", (uint) p);
462 printf("DRAM test passed.\n");
467 #if defined(CONFIG_PCI)
470 * Initialize PCI Devices, report devices found.
473 #ifndef CONFIG_PCI_PNP
474 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
475 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
476 PCI_IDSEL_NUMBER, PCI_ANY_ID,
477 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
479 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
485 static struct pci_controller hose = {
486 #ifndef CONFIG_PCI_PNP
487 config_table: pci_mpc85xxcds_config_table,
491 #endif /* CONFIG_PCI */
497 extern void pci_mpc85xx_init(struct pci_controller *hose);
499 pci_mpc85xx_init(&hose);