2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_85xx.h>
29 #include "../common/cadmus.h"
30 #include "../common/eeprom.h"
32 #if defined(CONFIG_DDR_ECC)
33 extern void ddr_enable_ecc(unsigned int dram_size);
36 extern long int spd_sdram(void);
38 void local_bus_init(void);
39 void sdram_init(void);
41 int board_early_init_f (void)
48 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
49 volatile ccsr_gur_t *gur = &immap->im_gur;
51 /* PCI slot in USER bits CSR[6:7] by convention. */
52 uint pci_slot = get_pci_slot ();
54 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
55 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
56 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
57 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
59 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
61 uint cpu_board_rev = get_cpu_board_revision ();
63 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
64 get_board_version (), pci_slot);
66 printf ("CPU Board Revision %d.%d (0x%04x)\n",
67 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
68 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
70 printf (" PCI1: %d bit, %s MHz, %s\n",
72 (pci1_speed == 33000000) ? "33" :
73 (pci1_speed == 66000000) ? "66" : "unknown",
74 pci1_clk_sel ? "sync" : "async");
77 printf (" PCI2: 32 bit, 66 MHz, %s\n",
78 pci2_clk_sel ? "sync" : "async");
80 printf (" PCI2: disabled\n");
84 * Initialize local bus.
92 initdram(int board_type)
95 volatile immap_t *immap = (immap_t *)CFG_IMMR;
97 puts("Initializing\n");
99 #if defined(CONFIG_DDR_DLL)
102 * Work around to stabilize DDR DLL MSYNC_IN.
103 * Errata DDR9 seems to have been fixed.
104 * This is now the workaround for Errata DDR11:
105 * Override DLL = 1, Course Adj = 1, Tap Select = 0
108 volatile ccsr_gur_t *gur= &immap->im_gur;
110 gur->ddrdllcr = 0x81000000;
111 asm("sync;isync;msync");
115 dram_size = spd_sdram();
117 #if defined(CONFIG_DDR_ECC)
119 * Initialize and enable DDR ECC.
121 ddr_enable_ecc(dram_size);
124 * SDRAM Initialization
133 * Initialize Local Bus
138 volatile immap_t *immap = (immap_t *)CFG_IMMR;
139 volatile ccsr_gur_t *gur = &immap->im_gur;
140 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
149 * Fix Local Bus clock glitch when DLL is enabled.
151 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
152 * If localbus freq is > 133Mhz, DLL can be safely enabled.
153 * Between 66 and 133, the DLL is enabled with an override workaround.
156 get_sys_info(&sysinfo);
157 clkdiv = lbc->lcrr & 0x0f;
158 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
161 lbc->lcrr |= 0x80000000; /* DLL Bypass */
163 } else if (lbc_hz >= 133) {
164 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
167 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
171 * Sample LBC DLL ctrl reg, upshift it to set the
174 temp_lbcdll = gur->lbcdllcr;
175 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
176 asm("sync;isync;msync");
181 * Initialize SDRAM memory on the Local Bus.
186 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
189 volatile immap_t *immap = (immap_t *)CFG_IMMR;
190 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
191 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
197 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
200 * Setup SDRAM Base and Option Registers
202 lbc->or2 = CFG_OR2_PRELIM;
205 lbc->br2 = CFG_BR2_PRELIM;
208 lbc->lbcr = CFG_LBC_LBCR;
211 lbc->lsrt = CFG_LBC_LSRT;
212 lbc->mrtpr = CFG_LBC_MRTPR;
216 * Determine which address lines to use baed on CPU board rev.
218 cpu_board_rev = get_cpu_board_revision();
219 lsdmr_common = CFG_LBC_LSDMR_COMMON;
220 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
221 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
222 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
223 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
226 * Assume something unable to identify itself is
227 * really old, and likely has lines 16/17 mapped.
229 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
233 * Issue PRECHARGE ALL command.
235 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
238 ppcDcbf((unsigned long) sdram_addr);
242 * Issue 8 AUTO REFRESH commands.
244 for (idx = 0; idx < 8; idx++) {
245 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
248 ppcDcbf((unsigned long) sdram_addr);
253 * Issue 8 MODE-set command.
255 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
258 ppcDcbf((unsigned long) sdram_addr);
262 * Issue NORMAL OP command.
264 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
267 ppcDcbf((unsigned long) sdram_addr);
268 udelay(200); /* Overkill. Must wait > 200 bus cycles */
270 #endif /* enable SDRAM init */
273 #if defined(CFG_DRAM_TEST)
277 uint *pstart = (uint *) CFG_MEMTEST_START;
278 uint *pend = (uint *) CFG_MEMTEST_END;
281 printf("Testing DRAM from 0x%08x to 0x%08x\n",
285 printf("DRAM test phase 1:\n");
286 for (p = pstart; p < pend; p++)
289 for (p = pstart; p < pend; p++) {
290 if (*p != 0xaaaaaaaa) {
291 printf ("DRAM test fails at: %08x\n", (uint) p);
296 printf("DRAM test phase 2:\n");
297 for (p = pstart; p < pend; p++)
300 for (p = pstart; p < pend; p++) {
301 if (*p != 0x55555555) {
302 printf ("DRAM test fails at: %08x\n", (uint) p);
307 printf("DRAM test passed.\n");
312 #if defined(CONFIG_PCI)
315 * Initialize PCI Devices, report devices found.
318 #ifndef CONFIG_PCI_PNP
319 static struct pci_config_table pci_mpc85xxcds_config_table[] = {
320 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
321 PCI_IDSEL_NUMBER, PCI_ANY_ID,
322 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
324 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
330 static struct pci_controller hose = {
331 #ifndef CONFIG_PCI_PNP
332 config_table: pci_mpc85xxcds_config_table,
336 #endif /* CONFIG_PCI */
342 extern void pci_mpc85xx_init(struct pci_controller *hose);
344 pci_mpc85xx_init(&hose);